diff --git a/bin/csh/dot.cshrc b/bin/csh/dot.cshrc index 3d1ddb094c72..2af8c36aef03 100644 --- a/bin/csh/dot.cshrc +++ b/bin/csh/dot.cshrc @@ -10,6 +10,11 @@ alias j jobs -l alias la ls -aF alias lf ls -FA alias ll ls -lAF +alias l ls -lsa +alias p ps -ax +alias d df -h +alias m more +alias tf tail -f # read(2) of directories may not be desirable by default, as this will provoke # EISDIR errors from each directory encountered. diff --git a/etc/master.passwd b/etc/master.passwd index 416b2b4e4874..11707f401e5a 100644 --- a/etc/master.passwd +++ b/etc/master.passwd @@ -1,4 +1,4 @@ -root::0:0::0:0:Charlie &:/root:/bin/sh +root::0:0::0:0:Charlie &:/root:/bin/csh toor:*:0:0::0:0:Bourne-again Superuser:/root: daemon:*:1:1::0:0:Owner of many system processes:/root:/usr/sbin/nologin operator:*:2:5::0:0:System &:/:/usr/sbin/nologin diff --git a/share/skel/dot.cshrc b/share/skel/dot.cshrc index c3c035d08955..716d3120ed2c 100644 --- a/share/skel/dot.cshrc +++ b/share/skel/dot.cshrc @@ -10,6 +10,11 @@ alias j jobs -l alias la ls -aF alias lf ls -FA alias ll ls -lAF +alias l ls -lsa +alias p ps -ax +alias d df -h +alias m more +alias tf tail -f # These are normally set through /etc/login.conf. You may override them here # if wanted. diff --git a/sys/arm64/conf/std.nvidia b/sys/arm64/conf/std.nvidia index fa12fdf8b90d..71b882e2b404 100644 --- a/sys/arm64/conf/std.nvidia +++ b/sys/arm64/conf/std.nvidia @@ -10,7 +10,7 @@ device uart_ns8250 # ns8250-type UART driver device uart_snps # Ethernet NICs -device re # RealTek 8139C+/8169/8169S/8110S +#device re # RealTek 8139C+/8169/8169S/8110S # USB support device tegra210_xusb_fw # Tegra XUSB firmware diff --git a/sys/arm64/rockchip/clk/rk3568_cru.c b/sys/arm64/rockchip/clk/rk3568_cru.c index 4b91e066dcf0..4c6c3fd13290 100644 --- a/sys/arm64/rockchip/clk/rk3568_cru.c +++ b/sys/arm64/rockchip/clk/rk3568_cru.c @@ -2,6 +2,7 @@ * SPDX-License-Identifier: BSD-2-Clause * * Copyright (c) 2021, 2022 Soren Schmidt + * Copyright (c) 2023, Emmanuel Vadot * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -47,12 +48,10 @@ #define RK3568_PLLSEL_CON(x) ((x) * 0x20) -#define RK3568_CLKSEL_CON(x) ((x) * 0x4 + 0x100) -#define RK3568_CLKGATE_CON(x) ((x) * 0x4 + 0x300) +#define CRU_CLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define CRU_CLKGATE_CON(x) ((x) * 0x4 + 0x300) #define RK3568_SOFTRST_CON(x) ((x) * 0x4 + 0x400) -#define PNAME(_name) static const char *_name[] - #define RK_PLLRATE(_hz, _ref, _fb, _post1, _post2, _dspd) \ { \ .freq = _hz, \ @@ -80,165 +79,6 @@ }, \ } -/* Clock for ARM core(s) */ -#define RK_ARMDIV(_id, _nm, _pn, _r, _off, _ds, _dw, _ms, _mw, _mp, _ap)\ -{ \ - .type = RK_CLK_ARMCLK, \ - .clk.armclk = &(struct rk_clk_armclk_def) { \ - .clkdef.id = _id, \ - .clkdef.name = _nm, \ - .clkdef.parent_names = _pn, \ - .clkdef.parent_cnt = nitems(_pn), \ - .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ - .muxdiv_offset = RK3568_CLKSEL_CON(_off), \ - .mux_shift = _ms, \ - .mux_width = _mw, \ - .div_shift = _ds, \ - .div_width = _dw, \ - .main_parent = _mp, \ - .alt_parent = _ap, \ - .rates = _r, \ - .nrates = nitems(_r), \ - }, \ -} - -/* Composite */ -#define RK_COMPOSITE(_id, _name, _pnames, _o, _ms, _mw, _ds, _dw, _go, _gw,_f)\ -{ \ - .type = RK_CLK_COMPOSITE, \ - .clk.composite = &(struct rk_clk_composite_def) { \ - .clkdef.id = _id, \ - .clkdef.name = _name, \ - .clkdef.parent_names = _pnames, \ - .clkdef.parent_cnt = nitems(_pnames), \ - .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ - .muxdiv_offset = RK3568_CLKSEL_CON(_o), \ - .mux_shift = _ms, \ - .mux_width = _mw, \ - .div_shift = _ds, \ - .div_width = _dw, \ - .gate_offset = RK3568_CLKGATE_CON(_go), \ - .gate_shift = _gw, \ - .flags = RK_CLK_COMPOSITE_HAVE_MUX | \ - RK_CLK_COMPOSITE_HAVE_GATE | _f, \ - }, \ -} - -/* Composite no mux */ -#define RK_COMPNOMUX(_id, _name, _pname, _o, _ds, _dw, _go, _gw, _f) \ -{ \ - .type = RK_CLK_COMPOSITE, \ - .clk.composite = &(struct rk_clk_composite_def) { \ - .clkdef.id = _id, \ - .clkdef.name = _name, \ - .clkdef.parent_names = (const char *[]){_pname}, \ - .clkdef.parent_cnt = 1, \ - .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ - .muxdiv_offset = RK3568_CLKSEL_CON(_o), \ - .div_shift = _ds, \ - .div_width = _dw, \ - .gate_offset = RK3568_CLKGATE_CON(_go), \ - .gate_shift = _gw, \ - .flags = RK_CLK_COMPOSITE_HAVE_GATE | _f, \ - }, \ -} - -/* Composite no div */ -#define RK_COMPNODIV(_id, _name, _pnames, _o, _ms, _mw, _go, _gw, _f) \ -{ \ - .type = RK_CLK_COMPOSITE, \ - .clk.composite = &(struct rk_clk_composite_def) { \ - .clkdef.id = _id, \ - .clkdef.name = _name, \ - .clkdef.parent_names = _pnames, \ - .clkdef.parent_cnt = nitems(_pnames), \ - .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ - .muxdiv_offset = RK3568_CLKSEL_CON(_o), \ - .mux_shift = _ms, \ - .mux_width = _mw, \ - .gate_offset = RK3568_CLKGATE_CON(_go), \ - .gate_shift = _gw, \ - .flags = RK_CLK_COMPOSITE_HAVE_MUX | \ - RK_CLK_COMPOSITE_HAVE_GATE | _f, \ - }, \ -} - -/* Composite div only */ -#define RK_COMPDIV(_id, _name, _pname, _o, _ds, _dw, _f) \ -{ \ - .type = RK_CLK_COMPOSITE, \ - .clk.composite = &(struct rk_clk_composite_def) { \ - .clkdef.id = _id, \ - .clkdef.name = _name, \ - .clkdef.parent_names = (const char *[]){_pname}, \ - .clkdef.parent_cnt = 1, \ - .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ - .muxdiv_offset = RK3568_CLKSEL_CON(_o), \ - .div_shift = _ds, \ - .div_width = _dw, \ - .flags = _f, \ - }, \ -} - - -/* Fixed factor mux/div */ -#define RK_FACTOR(_id, _name, _pname, _mult, _div) \ -{ \ - .type = RK_CLK_FIXED, \ - .clk.fixed = &(struct clk_fixed_def) { \ - .clkdef.id = _id, \ - .clkdef.name = _name, \ - .clkdef.parent_names = (const char *[]){_pname}, \ - .clkdef.parent_cnt = 1, \ - .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ - .mult = _mult, \ - .div = _div, \ - }, \ -} - -/* Fractional */ -#define RK_FRACTION(_id, _name, _pname, _o, _go, _gw, _f) \ -{ \ - .type = RK_CLK_FRACT, \ - .clk.fract = &(struct rk_clk_fract_def) { \ - .clkdef.id = _id, \ - .clkdef.name = _name, \ - .clkdef.parent_names = (const char *[]){_pname}, \ - .clkdef.parent_cnt = 1, \ - .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ - .offset = RK3568_CLKSEL_CON(_o), \ - .gate_offset = RK3568_CLKGATE_CON(_go), \ - .gate_shift = _gw, \ - .flags = RK_CLK_FRACT_HAVE_GATE | _f, \ - }, \ -} - -/* Multiplexer */ -#define RK_MUX(_id, _name, _pnames, _o, _ms, _mw, _f) \ -{ \ - .type = RK_CLK_MUX, \ - .clk.mux = &(struct rk_clk_mux_def) { \ - .clkdef.id = _id, \ - .clkdef.name = _name, \ - .clkdef.parent_names = _pnames, \ - .clkdef.parent_cnt = nitems(_pnames), \ - .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ - .offset = RK3568_CLKSEL_CON(_o), \ - .shift = _ms, \ - .width = _mw, \ - .mux_flags = _f, \ - }, \ -} - -#define RK_GATE(_id, _name, _pname, _o, _s) \ -{ \ - .id = _id, \ - .name = _name, \ - .parent_name = _pname, \ - .offset = RK3568_CLKGATE_CON(_o), \ - .shift = _s, \ -} - struct rk_clk_pll_rate rk3568_pll_rates[] = { /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd */ RK_PLLRATE(2208000000, 1, 92, 1, 1, 1), @@ -322,113 +162,114 @@ static struct rk_clk_armclk_rates rk3568_armclk_rates[] = { }; /* Parent clock defines */ -PNAME(mux_pll_p) = { "xin24m" }; -PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" }; -PNAME(mux_armclk_p) = { "apll", "gpll" }; -PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", +#define PLIST(_name) static const char *_name[] +PLIST(mux_pll_p) = { "xin24m" }; +PLIST(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" }; +PLIST(mux_armclk_p) = { "apll", "gpll" }; +PLIST(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_osc0_half" }; -PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", +PLIST(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_osc0_half" }; -PNAME(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", +PLIST(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin_osc0_half" }; -PNAME(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", +PLIST(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "i2s1_mclkin", "xin_osc0_half" }; -PNAME(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", +PLIST(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", "xin_osc0_half"}; -PNAME(clk_i2s3_2ch_tx_p) = { "clk_i2s3_2ch_tx_src", "clk_i2s3_2ch_tx_frac", +PLIST(clk_i2s3_2ch_tx_p) = { "clk_i2s3_2ch_tx_src", "clk_i2s3_2ch_tx_frac", "i2s3_mclkin", "xin_osc0_half" }; -PNAME(clk_i2s3_2ch_rx_p) = { "clk_i2s3_2ch_rx_src", "clk_i2s3_2ch_rx_frac", +PLIST(clk_i2s3_2ch_rx_p) = { "clk_i2s3_2ch_rx_src", "clk_i2s3_2ch_rx_frac", "i2s3_mclkin", "xin_osc0_half" }; -PNAME(mclk_spdif_8ch_p) = { "mclk_spdif_8ch_src", "mclk_spdif_8ch_frac" }; -PNAME(sclk_audpwm_p) = { "sclk_audpwm_src", "sclk_audpwm_frac" }; -PNAME(sclk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" }; -PNAME(sclk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" }; -PNAME(sclk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" }; -PNAME(sclk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" }; -PNAME(sclk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" }; -PNAME(sclk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" }; -PNAME(sclk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" }; -PNAME(sclk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" }; -PNAME(sclk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" }; -PNAME(mpll_gpll_cpll_npll_p) = { "mpll", "gpll", "cpll", "npll" }; -PNAME(gpll_cpll_npll_p) = { "gpll", "cpll", "npll" }; -PNAME(npll_gpll_p) = { "npll", "gpll" }; -PNAME(cpll_gpll_p) = { "cpll", "gpll" }; -PNAME(gpll_cpll_p) = { "gpll", "cpll" }; -PNAME(gpll_cpll_npll_vpll_p) = { "gpll", "cpll", "npll", "vpll" }; -PNAME(apll_gpll_npll_p) = { "apll", "gpll", "npll" }; -PNAME(sclk_core_pre_p) = { "sclk_core_src", "npll" }; -PNAME(gpll150_gpll100_gpll75_xin24m_p) = { "gpll_150m", "gpll_100m", "gpll_75m", +PLIST(mclk_spdif_8ch_p) = { "mclk_spdif_8ch_src", "mclk_spdif_8ch_frac" }; +PLIST(sclk_audpwm_p) = { "sclk_audpwm_src", "sclk_audpwm_frac" }; +PLIST(sclk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" }; +PLIST(sclk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" }; +PLIST(sclk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" }; +PLIST(sclk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" }; +PLIST(sclk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" }; +PLIST(sclk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" }; +PLIST(sclk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" }; +PLIST(sclk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" }; +PLIST(sclk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" }; +PLIST(mpll_gpll_cpll_npll_p) = { "mpll", "gpll", "cpll", "npll" }; +PLIST(gpll_cpll_npll_p) = { "gpll", "cpll", "npll" }; +PLIST(npll_gpll_p) = { "npll", "gpll" }; +PLIST(cpll_gpll_p) = { "cpll", "gpll" }; +PLIST(gpll_cpll_p) = { "gpll", "cpll" }; +PLIST(gpll_cpll_npll_vpll_p) = { "gpll", "cpll", "npll", "vpll" }; +PLIST(apll_gpll_npll_p) = { "apll", "gpll", "npll" }; +PLIST(sclk_core_pre_p) = { "sclk_core_src", "npll" }; +PLIST(gpll150_gpll100_gpll75_xin24m_p) = { "clk_gpll_div_150m", "clk_gpll_div_100m", "clk_gpll_div_75m", "xin24m" }; -PNAME(clk_gpu_pre_mux_p) = { "clk_gpu_src", "gpu_pvtpll_out" }; -PNAME(clk_npu_pre_ndft_p) = { "clk_npu_src", "dummy"}; -PNAME(clk_npu_p) = { "clk_npu_pre_ndft", "npu_pvtpll_out" }; -PNAME(dpll_gpll_cpll_p) = { "dpll", "gpll", "cpll" }; -PNAME(clk_ddr1x_p) = { "clk_ddrphy1x_src", "dpll" }; -PNAME(gpll200_gpll150_gpll100_xin24m_p) = { "gpll_200m", "gpll_150m", - "gpll_100m", "xin24m" }; -PNAME(gpll100_gpll75_gpll50_p) = { "gpll_100m", "gpll_75m", "cpll_50m" }; -PNAME(i2s0_mclkout_tx_p) = { "clk_i2s0_8ch_tx", "xin_osc0_half" }; -PNAME(i2s0_mclkout_rx_p) = { "clk_i2s0_8ch_rx", "xin_osc0_half" }; -PNAME(i2s1_mclkout_tx_p) = { "clk_i2s1_8ch_tx", "xin_osc0_half" }; -PNAME(i2s1_mclkout_rx_p) = { "clk_i2s1_8ch_rx", "xin_osc0_half" }; -PNAME(i2s2_mclkout_p) = { "clk_i2s2_2ch", "xin_osc0_half" }; -PNAME(i2s3_mclkout_tx_p) = { "clk_i2s3_2ch_tx", "xin_osc0_half" }; -PNAME(i2s3_mclkout_rx_p) = { "clk_i2s3_2ch_rx", "xin_osc0_half" }; -PNAME(mclk_pdm_p) = { "gpll_300m", "cpll_250m", "gpll_200m", "gpll_100m" }; -PNAME(clk_i2c_p) = { "gpll_200m", "gpll_100m", "xin24m", "cpll_100m" }; -PNAME(gpll200_gpll150_gpll100_p) = { "gpll_200m", "gpll_150m", "gpll_100m" }; -PNAME(gpll300_gpll200_gpll100_p) = { "gpll_300m", "gpll_200m", "gpll_100m" }; -PNAME(clk_nandc_p) = { "gpll_200m", "gpll_150m", "cpll_100m", "xin24m" }; -PNAME(sclk_sfc_p) = { "xin24m", "cpll_50m", "gpll_75m", "gpll_100m", - "cpll_125m", "gpll_150m" }; -PNAME(gpll200_gpll150_cpll125_p) = { "gpll_200m", "gpll_150m", "cpll_125m" }; -PNAME(cclk_emmc_p) = { "xin24m", "gpll_200m", "gpll_150m", "cpll_100m", - "cpll_50m", "clk_osc0_div_375k" }; -PNAME(aclk_pipe_p) = { "gpll_400m", "gpll_300m", "gpll_200m", "xin24m" }; -PNAME(gpll200_cpll125_p) = { "gpll_200m", "cpll_125m" }; -PNAME(gpll300_gpll200_gpll100_xin24m_p) = { "gpll_300m", "gpll_200m", - "gpll_100m", "xin24m" }; -PNAME(clk_sdmmc_p) = { "xin24m", "gpll_400m", "gpll_300m", "cpll_100m", - "cpll_50m", "clk_osc0_div_750k" }; -PNAME(cpll125_cpll50_cpll25_xin24m_p) = { "cpll_125m", "cpll_50m", "cpll_25m", +PLIST(clk_gpu_pre_mux_p) = { "clk_gpu_src", "gpu_pvtpll_out" }; +PLIST(clk_npu_pre_ndft_p) = { "clk_npu_src", "clk_npu_np5"}; +PLIST(clk_npu_p) = { "clk_npu_pre_ndft", "npu_pvtpll_out" }; +PLIST(dpll_gpll_cpll_p) = { "dpll", "gpll", "cpll" }; +PLIST(clk_ddr1x_p) = { "clk_ddrphy1x_src", "dpll" }; +PLIST(gpll200_gpll150_gpll100_xin24m_p) = { "clk_gpll_div_200m", "clk_gpll_div_150m", + "clk_gpll_div_100m", "xin24m" }; +PLIST(gpll100_gpll75_gpll50_p) = { "clk_gpll_div_100m", "clk_gpll_div_75m", "clk_cpll_div_50m" }; +PLIST(i2s0_mclkout_tx_p) = { "clk_i2s0_8ch_tx", "xin_osc0_half" }; +PLIST(i2s0_mclkout_rx_p) = { "clk_i2s0_8ch_rx", "xin_osc0_half" }; +PLIST(i2s1_mclkout_tx_p) = { "clk_i2s1_8ch_tx", "xin_osc0_half" }; +PLIST(i2s1_mclkout_rx_p) = { "clk_i2s1_8ch_rx", "xin_osc0_half" }; +PLIST(i2s2_mclkout_p) = { "clk_i2s2_2ch", "xin_osc0_half" }; +PLIST(i2s3_mclkout_tx_p) = { "clk_i2s3_2ch_tx", "xin_osc0_half" }; +PLIST(i2s3_mclkout_rx_p) = { "clk_i2s3_2ch_rx", "xin_osc0_half" }; +PLIST(mclk_pdm_p) = { "clk_gpll_div_300m", "clk_cpll_div_250m", "clk_gpll_div_200m", "clk_gpll_div_100m" }; +PLIST(clk_i2c_p) = { "clk_gpll_div_200m", "clk_gpll_div_100m", "xin24m", "clk_cpll_div_100m" }; +PLIST(gpll200_gpll150_gpll100_p) = { "clk_gpll_div_200m", "clk_gpll_div_150m", "clk_gpll_div_100m" }; +PLIST(gpll300_gpll200_gpll100_p) = { "clk_gpll_div_300m", "clk_gpll_div_200m", "clk_gpll_div_100m" }; +PLIST(clk_nandc_p) = { "clk_gpll_div_200m", "clk_gpll_div_150m", "clk_cpll_div_100m", "xin24m" }; +PLIST(sclk_sfc_p) = { "xin24m", "clk_cpll_div_50m", "clk_gpll_div_75m", "clk_gpll_div_100m", + "clk_cpll_div_125m", "clk_gpll_div_150m" }; +PLIST(gpll200_gpll150_cpll125_p) = { "clk_gpll_div_200m", "clk_gpll_div_150m", "clk_cpll_div_125m" }; +PLIST(cclk_emmc_p) = { "xin24m", "clk_gpll_div_200m", "clk_gpll_div_150m", "clk_cpll_div_100m", + "clk_cpll_div_50m", "clk_osc0_div_375k" }; +PLIST(aclk_pipe_p) = { "clk_gpll_div_400m", "clk_gpll_div_300m", "clk_gpll_div_200m", "xin24m" }; +PLIST(gpll200_cpll125_p) = { "clk_gpll_div_200m", "clk_cpll_div_125m" }; +PLIST(gpll300_gpll200_gpll100_xin24m_p) = { "clk_gpll_div_300m", "clk_gpll_div_200m", + "clk_gpll_div_100m", "xin24m" }; +PLIST(clk_sdmmc_p) = { "xin24m", "clk_gpll_div_400m", "clk_gpll_div_300m", "clk_cpll_div_100m", + "clk_cpll_div_50m", "clk_osc0_div_750k" }; +PLIST(cpll125_cpll50_cpll25_xin24m_p) = { "clk_cpll_div_125m", "clk_cpll_div_50m", "clk_cpll_div_25m", "xin24m" }; -PNAME(clk_gmac_ptp_p) = { "cpll_62p5", "gpll_100m", "cpll_50m", "xin24m" }; -PNAME(cpll333_gpll300_gpll200_p) = { "cpll_333m", "gpll_300m", "gpll_200m" }; -PNAME(cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" }; -PNAME(gpll_usb480m_xin24m_p) = { "gpll", "usb480m", "xin24m", "xin24m" }; -PNAME(gpll300_cpll250_gpll100_xin24m_p) = { "gpll_300m", "cpll_250m", - "gpll_100m", "xin24m" }; -PNAME(cpll_gpll_hpll_vpll_p) = { "cpll", "gpll", "hpll", "vpll" }; -PNAME(hpll_vpll_gpll_cpll_p) = { "hpll", "vpll", "gpll", "cpll" }; -PNAME(gpll400_cpll333_gpll200_p) = { "gpll_400m", "cpll_333m", "gpll_200m" }; -PNAME(gpll100_gpll75_cpll50_xin24m_p) = { "gpll_100m", "gpll_75m", "cpll_50m", +PLIST(clk_gmac_ptp_p) = { "clk_cpll_div_62P5m", "clk_gpll_div_100m", "clk_cpll_div_50m", "xin24m" }; +PLIST(cpll333_gpll300_gpll200_p) = { "clk_cpll_div_333m", "clk_gpll_div_300m", "clk_gpll_div_200m" }; +PLIST(cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" }; +PLIST(gpll_usb480m_xin24m_p) = { "gpll", "usb480m", "xin24m", "xin24m" }; +PLIST(gpll300_cpll250_gpll100_xin24m_p) = { "clk_gpll_div_300m", "clk_cpll_div_250m", + "clk_gpll_div_100m", "xin24m" }; +PLIST(cpll_gpll_hpll_vpll_p) = { "cpll", "gpll", "hpll", "vpll" }; +PLIST(hpll_vpll_gpll_cpll_p) = { "hpll", "vpll", "gpll", "cpll" }; +PLIST(gpll400_cpll333_gpll200_p) = { "clk_gpll_div_400m", "clk_cpll_div_333m", "clk_gpll_div_200m" }; +PLIST(gpll100_gpll75_cpll50_xin24m_p) = { "clk_gpll_div_100m", "clk_gpll_div_75m", "clk_cpll_div_50m", "xin24m" }; -PNAME(xin24m_gpll100_cpll100_p) = { "xin24m", "gpll_100m", "cpll_100m" }; -PNAME(gpll_cpll_usb480m_p) = { "gpll", "cpll", "usb480m" }; -PNAME(gpll100_xin24m_cpll100_p) = { "gpll_100m", "xin24m", "cpll_100m" }; -PNAME(gpll200_xin24m_cpll100_p) = { "gpll_200m", "xin24m", "cpll_100m" }; -PNAME(xin24m_32k_p) = { "xin24m", "clk_rtc_32k" }; -PNAME(cpll500_gpll400_gpll300_xin24m_p) = { "cpll_500m", "gpll_400m", - "gpll_300m", "xin24m" }; -PNAME(gpll400_gpll300_gpll200_xin24m_p) = { "gpll_400m", "gpll_300m", - "gpll_200m", "xin24m" }; -PNAME(xin24m_cpll100_p) = { "xin24m", "cpll_100m" }; -PNAME(mux_gmac0_p) = { "clk_mac0_2top", "gmac0_clkin" }; -PNAME(mux_gmac0_rgmii_speed_p) = { "clk_gmac0", "clk_gmac0", +PLIST(xin24m_gpll100_cpll100_p) = { "xin24m", "clk_gpll_div_100m", "clk_cpll_div_100m" }; +PLIST(gpll_cpll_usb480m_p) = { "gpll", "cpll", "usb480m" }; +PLIST(gpll100_xin24m_cpll100_p) = { "clk_gpll_div_100m", "xin24m", "clk_cpll_div_100m" }; +PLIST(gpll200_xin24m_cpll100_p) = { "clk_gpll_div_200m", "xin24m", "clk_cpll_div_100m" }; +PLIST(xin24m_32k_p) = { "xin24m", "clk_rtc_32k" }; +PLIST(cpll500_gpll400_gpll300_xin24m_p) = { "clk_cpll_div_500m", "clk_gpll_div_400m", + "clk_gpll_div_300m", "xin24m" }; +PLIST(gpll400_gpll300_gpll200_xin24m_p) = { "clk_gpll_div_400m", "clk_gpll_div_300m", + "clk_gpll_div_200m", "xin24m" }; +PLIST(xin24m_cpll100_p) = { "xin24m", "clk_cpll_div_100m" }; +PLIST(mux_gmac0_p) = { "clk_mac0_2top", "gmac0_clkin" }; +PLIST(mux_gmac0_rgmii_speed_p) = { "clk_gmac0", "clk_gmac0", "clk_gmac0_tx_div50", "clk_gmac0_tx_div5" }; -PNAME(mux_gmac0_rmii_speed_p) = { "clk_gmac0_rx_div20", "clk_gmac0_rx_div2" }; -PNAME(mux_gmac0_rx_tx_p) = { "clk_gmac0_rgmii_speed", "clk_gmac0_rmii_speed", +PLIST(mux_gmac0_rmii_speed_p) = { "clk_gmac0_rx_div20", "clk_gmac0_rx_div2" }; +PLIST(mux_gmac0_rx_tx_p) = { "clk_gmac0_rgmii_speed", "clk_gmac0_rmii_speed", "clk_gmac0_xpcs_mii" }; -PNAME(mux_gmac1_p) = { "clk_mac1_2top", "gmac1_clkin" }; -PNAME(mux_gmac1_rgmii_speed_p) = { "clk_gmac1", "clk_gmac1", +PLIST(mux_gmac1_p) = { "clk_mac1_2top", "gmac1_clkin" }; +PLIST(mux_gmac1_rgmii_speed_p) = { "clk_gmac1", "clk_gmac1", "clk_gmac1_tx_div50", "clk_gmac1_tx_div5" }; -PNAME(mux_gmac1_rmii_speed_p) = { "clk_gmac1_rx_div20", "clk_gmac1_rx_div2" }; -PNAME(mux_gmac1_rx_tx_p) = { "clk_gmac1_rgmii_speed", "clk_gmac1_rmii_speed", +PLIST(mux_gmac1_rmii_speed_p) = { "clk_gmac1_rx_div20", "clk_gmac1_rx_div2" }; +PLIST(mux_gmac1_rx_tx_p) = { "clk_gmac1_rgmii_speed", "clk_gmac1_rmii_speed", "clk_gmac1_xpcs_mii" }; -PNAME(clk_mac_2top_p) = { "cpll_125m", "cpll_50m", "cpll_25m", "ppll" }; -PNAME(aclk_rkvdec_pre_p) = { "gpll", "cpll" }; -PNAME(clk_rkvdec_core_p) = { "gpll", "cpll", "npll", "vpll" }; +PLIST(clk_mac_2top_p) = { "clk_cpll_div_125m", "clk_cpll_div_50m", "clk_cpll_div_25m", "ppll" }; +PLIST(aclk_rkvdec_pre_p) = { "gpll", "cpll" }; +PLIST(clk_rkvdec_core_p) = { "gpll", "cpll", "npll", "vpll" }; /* CLOCKS */ static struct rk_clk rk3568_clks[] = { @@ -436,7 +277,7 @@ static struct rk_clk rk3568_clks[] = { LINK("xin24m"), LINK("clk_rtc_32k"), LINK("usb480m_phy"), - LINK("mpll"), // SOS SCRU + LINK("mpll"), /* It lives in SCRU */ LINK("i2s0_mclkin"), LINK("i2s1_mclkin"), LINK("i2s2_mclkin"), @@ -456,563 +297,1100 @@ static struct rk_clk rk3568_clks[] = { RK_PLL(PLL_CPLL, "cpll", mux_pll_p, 3, 4), RK_PLL(PLL_NPLL, "npll", mux_pll_p, 4, 10), RK_PLL(PLL_VPLL, "vpll", mux_pll_p, 5, 12), - RK_ARMDIV(ARMCLK, "armclk", mux_armclk_p, rk3568_armclk_rates, 0, 0, 5, + ARMDIV(ARMCLK, "armclk", mux_armclk_p, rk3568_armclk_rates, 0, 0, 5, 6, 1, 0, 1), - RK_FACTOR(0, "clk_osc0_div_375k", "clk_osc0_div_750k", 1, 2), - RK_FACTOR(0, "xin_osc0_half", "xin24m", 1, 2), - RK_MUX(USB480M, "usb480m", mux_usb480m_p, -16, 14, 2, 0), + FFACT(0, "clk_osc0_div_375k", "clk_osc0_div_750k", 1, 2), + FFACT(0, "xin_osc0_half", "xin24m", 1, 2), + MUX(USB480M, "usb480m", mux_usb480m_p, 0, -16, 14, 2), /* Clocks */ - RK_COMPNOMUX(0, "gpll_400m", "gpll", 75, 0, 5, 35, 0, 0), - RK_COMPNOMUX(0, "gpll_300m", "gpll", 75, 8, 5, 35, 1, 0), - RK_COMPNOMUX(0, "gpll_200m", "gpll", 76, 0, 5, 35, 2, 0), - RK_COMPNOMUX(0, "gpll_150m", "gpll", 76, 8, 5, 35, 3, 0), - RK_COMPNOMUX(0, "gpll_100m", "gpll", 77, 0, 5, 35, 4, 0), - RK_COMPNOMUX(0, "gpll_75m", "gpll", 77, 8, 5, 35, 5, 0), - RK_COMPNOMUX(0, "gpll_20m", "gpll", 78, 0, 6, 35, 6, 0), - RK_COMPNOMUX(CPLL_500M, "cpll_500m", "cpll", 78, 8, 5, 35, 7, 0), - RK_COMPNOMUX(CPLL_333M, "cpll_333m", "cpll", 79, 0, 5, 35, 8, 0), - RK_COMPNOMUX(CPLL_250M, "cpll_250m", "cpll", 79, 8, 5, 35, 9, 0), - RK_COMPNOMUX(CPLL_125M, "cpll_125m", "cpll", 80, 0, 5, 35, 10, 0), - RK_COMPNOMUX(CPLL_100M, "cpll_100m", "cpll", 82, 0, 5, 35, 11, 0), - RK_COMPNOMUX(CPLL_62P5M, "cpll_62p5", "cpll", 80, 8, 5, 35, 12, 0), - RK_COMPNOMUX(CPLL_50M, "cpll_50m", "cpll", 81, 0, 5, 35, 13, 0), - RK_COMPNOMUX(CPLL_25M, "cpll_25m", "cpll", 81, 8, 6, 35, 14, 0), - RK_COMPNOMUX(0, "clk_osc0_div_750k", "xin24m", 82, 8, 6, 35, 15, 0), - RK_COMPOSITE(0, "sclk_core_src", apll_gpll_npll_p, 2, 8, 2, 0, 4, 0, - 5, 0), - RK_COMPNODIV(0, "sclk_core", sclk_core_pre_p, 2, 15, 1, 0, 7, 0), - RK_COMPNOMUX(0, "atclk_core", "armclk", 3, 0, 5, 0, 8, 0), - RK_COMPNOMUX(0, "gicclk_core", "armclk", 3, 8, 5, 0, 9, 0), - RK_COMPNOMUX(0, "pclk_core_pre", "armclk", 4, 0, 5, 0, 10, 0), - RK_COMPNOMUX(0, "periphclk_core_pre", "armclk", 4, 8, 5, 0, 11, 0), - RK_COMPNOMUX(0, "tsclk_core", "periphclk_core_pre", 5, 0, 4, 0, 14, 0), - RK_COMPNOMUX(0, "cntclk_core", "periphclk_core_pre", 5, 4, 4, 0, 15, 0), - RK_COMPNOMUX(0, "aclk_core", "sclk_core", 5, 8, 5, 1, 0, 0), - RK_COMPNODIV(ACLK_CORE_NIU2BUS, "aclk_core_niu2bus", - gpll150_gpll100_gpll75_xin24m_p, 5, 14, 2, 1, 2, 0), - RK_COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", mpll_gpll_cpll_npll_p, 6, 6, 2, - 0, 4, 2, 0, 0), - RK_MUX(CLK_GPU_PRE_MUX, "clk_gpu_pre_mux", clk_gpu_pre_mux_p, 6, 11, - 1, 0), - RK_COMPDIV(ACLK_GPU_PRE, "aclk_gpu_pre", "clk_gpu_pre_mux", 6, 8, 2, 0), - RK_COMPDIV(PCLK_GPU_PRE, "pclk_gpu_pre", "clk_gpu_pre_mux", 6, 12, 4,0), - RK_COMPOSITE(CLK_NPU_SRC, "clk_npu_src", npll_gpll_p, 7, 6, 1, 0, 4, 3, - 0, 0), - RK_MUX(CLK_NPU_PRE_NDFT, "clk_npu_pre_ndft", clk_npu_pre_ndft_p, 7, 8, - 1, 0), - RK_MUX(CLK_NPU, "clk_npu", clk_npu_p, 7, 15, 1, 0), - RK_COMPNOMUX(HCLK_NPU_PRE, "hclk_npu_pre", "clk_npu", 8, 0, 4, 3, 2, 0), - RK_COMPNOMUX(PCLK_NPU_PRE, "pclk_npu_pre", "clk_npu", 8, 4, 4, 3, 3, 0), - RK_COMPOSITE(CLK_DDRPHY1X_SRC, "clk_ddrphy1x_src", dpll_gpll_cpll_p, 9, - 6, 2, 0, 5, 4, 0, 0), - RK_MUX(CLK_DDR1X, "clk_ddr1x", clk_ddr1x_p, 9, 15, 1, - RK_CLK_COMPOSITE_GRF), - RK_COMPNOMUX(CLK_MSCH, "clk_msch", "clk_ddr1x", 10, 0, 2, 4, 2, 0), - RK_COMPNODIV(ACLK_GIC_AUDIO, "aclk_gic_audio", - gpll200_gpll150_gpll100_xin24m_p, 10, 8, 2, 5, 0, 0), - RK_COMPNODIV(HCLK_GIC_AUDIO, "hclk_gic_audio", - gpll150_gpll100_gpll75_xin24m_p, 10, 10, 2, 5, 1, 0), - RK_COMPNODIV(DCLK_SDMMC_BUFFER, "dclk_sdmmc_buffer", - gpll100_gpll75_gpll50_p, 10, 12, 2, 5, 9, 0), - RK_COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", - gpll_cpll_npll_p, 11, 8, 2, 0, 7, 6, 0, 0), - RK_MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, 11, 10, - 2, 0), - RK_FRACTION(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", - "clk_i2s0_8ch_tx_src", 12, 6, 1, 0), - RK_COMPNODIV(I2S0_MCLKOUT_TX, "i2s0_mclkout_tx", i2s0_mclkout_tx_p, 11, - 15, 1, 6, 3, 0), - RK_COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", - gpll_cpll_npll_p, 13, 8, 2, 0, 7, 6, 4, 0), - RK_MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, 13, 10, - 2, 0), - RK_FRACTION(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", - "clk_i2s0_8ch_rx_src", 14, 6, 5, 0), - RK_COMPNODIV(I2S0_MCLKOUT_RX, "i2s0_mclkout_rx", i2s0_mclkout_rx_p, 13, - 15, 1, 6, 7, 0), - RK_COMPOSITE(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", - gpll_cpll_npll_p, 15, 8, 2, 0, 7, 6, 8, 0), - RK_MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, 15, 10, - 2, 0), - RK_FRACTION(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", - "clk_i2s1_8ch_tx_src", 16, 6, 9, 0), - RK_COMPNODIV(I2S1_MCLKOUT_TX, "i2s1_mclkout_tx", i2s1_mclkout_tx_p, 15, - 15, 1, 6, 11, 0), - RK_COMPOSITE(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", - gpll_cpll_npll_p, 17, 8, 2, 0, 7, 6, 12, 0), - RK_MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, 17, 10, - 2, 0), - RK_FRACTION(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", - "clk_i2s1_8ch_rx_src", 18, 6, 13, 0), - RK_COMPNODIV(I2S1_MCLKOUT_RX, "i2s1_mclkout_rx", i2s1_mclkout_rx_p, 17, - 15, 1, 6, 15, 0), - RK_COMPOSITE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", gpll_cpll_npll_p, 19, - 8, 2, 0, 7, 7, 0, 0), - RK_MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, 19, 10, 2, 0), - RK_FRACTION(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", - 20, 7, 1, 0), - RK_COMPNODIV(I2S2_MCLKOUT, "i2s2_mclkout", i2s2_mclkout_p, 19, 15, 1, 7, - 3, 0), - RK_COMPOSITE(CLK_I2S3_2CH_TX_SRC, "clk_i2s3_2ch_tx_src", - gpll_cpll_npll_p, 21, 8, 2, 0, 7, 7, 4, 0), - RK_MUX(CLK_I2S3_2CH_TX, "clk_i2s3_2ch_tx", clk_i2s3_2ch_tx_p, 21, 10, - 2, 0), - RK_FRACTION(CLK_I2S3_2CH_TX_FRAC, "clk_i2s3_2ch_tx_frac", - "clk_i2s3_2ch_tx_src", 22, 7, 5, 0), - RK_COMPNODIV(I2S3_MCLKOUT_TX, "i2s3_mclkout_tx", i2s3_mclkout_tx_p, 21, - 15, 1, 7, 7, 0), - RK_COMPOSITE(CLK_I2S3_2CH_RX_SRC, "clk_i2s3_2ch_rx_src", - gpll_cpll_npll_p, 83, 8, 2, 0, 7, 7, 8, 0), - RK_MUX(CLK_I2S3_2CH_RX, "clk_i2s3_2ch_rx", clk_i2s3_2ch_rx_p, 83, 10, - 2, 0), - RK_FRACTION(CLK_I2S3_2CH_RX_FRAC, "clk_i2s3_2ch_rx_frac", - "clk_i2s3_2ch_rx_src", 84, 7, 9, 0), - RK_COMPNODIV(I2S3_MCLKOUT_RX, "i2s3_mclkout_rx", i2s3_mclkout_rx_p, 83, - 15, 1, 7, 11, 0), - RK_COMPNODIV(MCLK_PDM, "mclk_pdm", mclk_pdm_p, 23, 8, 2, 5, 15, 0), - RK_COMPOSITE(MCLK_SPDIF_8CH_SRC, "mclk_spdif_8ch_src", cpll_gpll_p, 23, - 14, 1, 0, 7, 7, 14, 0), - RK_MUX(MCLK_SPDIF_8CH, "mclk_spdif_8ch", mclk_spdif_8ch_p, 23, 15, 1,0), - RK_FRACTION(MCLK_SPDIF_8CH_FRAC, "mclk_spdif_8ch_frac", - "mclk_spdif_8ch_src", 24, 7, 15, 0), - RK_COMPOSITE(SCLK_AUDPWM_SRC, "sclk_audpwm_src", gpll_cpll_p, 25, 14, 1, - 0, 6, 8, 1, 0), - RK_MUX(SCLK_AUDPWM, "sclk_audpwm", sclk_audpwm_p, 25, 15, 1, 0), - RK_FRACTION(SCLK_AUDPWM_FRAC, "sclk_audpwm_frac", "sclk_audpwm_src", 26, - 8, 2, 0), - RK_COMPNODIV(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", clk_i2c_p, 23, 10, 2, - 8, 4, 0), - RK_COMPNODIV(ACLK_SECURE_FLASH, "aclk_secure_flash", - gpll200_gpll150_gpll100_xin24m_p, 27, 0, 2, 8, 7, 0), - RK_COMPNODIV(HCLK_SECURE_FLASH, "hclk_secure_flash", - gpll150_gpll100_gpll75_xin24m_p, 27, 2, 2, 8, 8, 0), - RK_COMPNODIV(CLK_CRYPTO_NS_CORE, "clk_crypto_ns_core", - gpll200_gpll150_gpll100_p, 27, 4, 2, 8, 13, 0), - RK_COMPNODIV(CLK_CRYPTO_NS_PKA, "clk_crypto_ns_pka", - gpll300_gpll200_gpll100_p, 27, 6, 2, 8, 14, 0), - RK_COMPNODIV(NCLK_NANDC, "nclk_nandc", clk_nandc_p, 28, 0, 2, 9, 1, 0), - RK_COMPNODIV(SCLK_SFC, "sclk_sfc", sclk_sfc_p, 28, 4, 3, 9, 4, 0), - RK_COMPNODIV(BCLK_EMMC, "bclk_emmc", gpll200_gpll150_cpll125_p, 28, 8, - 2, 9, 7, 0), - RK_COMPNODIV(CCLK_EMMC, "cclk_emmc", cclk_emmc_p, 28, 12, 3, 9, 8, 0), - RK_COMPNODIV(ACLK_PIPE, "aclk_pipe", aclk_pipe_p, 29, 0, 2, 10, 0, 0), - RK_COMPNOMUX(PCLK_PIPE, "pclk_pipe", "aclk_pipe", 29, 4, 4, 10, 1, 0), - RK_COMPNODIV(CLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", xin24m_32k_p, - 29, 8, 1, 10, 10, 0), - RK_COMPNODIV(CLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", xin24m_32k_p, - 29, 9, 1, 10, 14, 0), - RK_COMPNODIV(CLK_XPCS_EEE, "clk_xpcs_eee", gpll200_cpll125_p, 29, 13, 1, - 10, 4, 0), - RK_COMPNODIV(ACLK_PHP, "aclk_php", gpll300_gpll200_gpll100_xin24m_p, 30, - 0, 2, 14, 8, 0), - RK_COMPNODIV(HCLK_PHP, "hclk_php", gpll150_gpll100_gpll75_xin24m_p, 30, - 2, 2, 14, 9, 0), - RK_COMPNOMUX(PCLK_PHP, "pclk_php", "aclk_php", 30, 4, 4, 14, 10, 0), - RK_COMPNODIV(CLK_SDMMC0, "clk_sdmmc0", clk_sdmmc_p, 30, 8, 3, 15, 1, 0), - RK_COMPNODIV(CLK_SDMMC1, "clk_sdmmc1", clk_sdmmc_p, 30, 12, 3, 15, 3,0), - RK_COMPNODIV(CLK_MAC0_2TOP, "clk_mac0_2top", clk_mac_2top_p, 31, 8, 2, - 15, 7, 0), - RK_COMPNODIV(CLK_MAC0_OUT, "clk_mac0_out", - cpll125_cpll50_cpll25_xin24m_p, 31, 14, 2, 15, 8, 0), - RK_COMPNODIV(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", clk_gmac_ptp_p, 31, - 12, 2, 15, 4, 0), - RK_MUX(SCLK_GMAC0, "clk_gmac0", mux_gmac0_p, 31, 2, 1, 0), - RK_FACTOR(0, "clk_gmac0_tx_div5", "clk_gmac0", 1, 5), - RK_FACTOR(0, "clk_gmac0_tx_div50", "clk_gmac0", 1, 50), - RK_FACTOR(0, "clk_gmac0_rx_div2", "clk_gmac0", 1, 2), - RK_FACTOR(0, "clk_gmac0_rx_div20", "clk_gmac0", 1, 20), - RK_MUX(SCLK_GMAC0_RGMII_SPEED, "clk_gmac0_rgmii_speed", - mux_gmac0_rgmii_speed_p, 31, 4, 2, 0), - RK_MUX(SCLK_GMAC0_RMII_SPEED, "clk_gmac0_rmii_speed", - mux_gmac0_rmii_speed_p, 31, 3, 1, 0), - RK_MUX(SCLK_GMAC0_RX_TX, "clk_gmac0_rx_tx", mux_gmac0_rx_tx_p, 31, 0, - 2, 0), - RK_COMPNODIV(ACLK_USB, "aclk_usb", gpll300_gpll200_gpll100_xin24m_p, 32, - 0, 2, 16, 0, 0), - RK_COMPNODIV(HCLK_USB, "hclk_usb", gpll150_gpll100_gpll75_xin24m_p, 32, - 2, 2, 16, 1, 0), - RK_COMPNOMUX(PCLK_USB, "pclk_usb", "aclk_usb", 32, 4, 4, 16, 2, 0), - RK_COMPNODIV(CLK_SDMMC2, "clk_sdmmc2", clk_sdmmc_p, 32, 8, 3, 17, 1, 0), - RK_COMPNODIV(CLK_MAC1_2TOP, "clk_mac1_2top", clk_mac_2top_p, 33, 8, 2, - 17, 5, 0), - RK_COMPNODIV(CLK_MAC1_OUT, "clk_mac1_out", - cpll125_cpll50_cpll25_xin24m_p, 33, 14, 2, 17, 6, 0), - RK_COMPNODIV(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", clk_gmac_ptp_p, 33, - 12, 2, 17, 2, 0), - RK_MUX(SCLK_GMAC1, "clk_gmac1", mux_gmac1_p, 33, 2, 1, 0), - RK_FACTOR(0, "clk_gmac1_tx_div5", "clk_gmac1", 1, 5), - RK_FACTOR(0, "clk_gmac1_tx_div50", "clk_gmac1", 1, 50), - RK_FACTOR(0, "clk_gmac1_rx_div2", "clk_gmac1", 1, 2), - RK_FACTOR(0, "clk_gmac1_rx_div20", "clk_gmac1", 1, 20), - RK_MUX(SCLK_GMAC1_RGMII_SPEED, "clk_gmac1_rgmii_speed", - mux_gmac1_rgmii_speed_p, 33, 4, 2, 0), - RK_MUX(SCLK_GMAC1_RMII_SPEED, "clk_gmac1_rmii_speed", - mux_gmac1_rmii_speed_p, 33, 3, 1, 0), - RK_MUX(SCLK_GMAC1_RX_TX, "clk_gmac1_rx_tx", mux_gmac1_rx_tx_p, 33, 0, - 2, 0), - RK_COMPNODIV(ACLK_PERIMID, "aclk_perimid", - gpll300_gpll200_gpll100_xin24m_p, 10, 4, 2, 14, 0, 0), - RK_COMPNODIV(HCLK_PERIMID, "hclk_perimid", - gpll150_gpll100_gpll75_xin24m_p, 10, 6, 2, 14, 1, 0), - RK_COMPNODIV(ACLK_VI, "aclk_vi", gpll400_gpll300_gpll200_xin24m_p, 34, - 0, 2, 18, 0, 0), - RK_COMPNOMUX(HCLK_VI, "hclk_vi", "aclk_vi", 34, 4, 4, 18, 1, 0), - RK_COMPNOMUX(PCLK_VI, "pclk_vi", "aclk_vi", 34, 8, 4, 18, 2, 0), - RK_COMPNODIV(DCLK_VICAP, "dclk_vicap", cpll333_gpll300_gpll200_p, 34, - 14, 2, 18, 11, 0), - RK_COMPOSITE(CLK_ISP, "clk_isp", cpll_gpll_hpll_p, 35, 6, 2, 0, 5, 19, - 2, 0), - RK_COMPOSITE(CLK_CIF_OUT, "clk_cif_out", gpll_usb480m_xin24m_p, 35, 14, - 2, 8, 6, 19, 8, 0), - RK_COMPOSITE(CLK_CAM0_OUT, "clk_cam0_out", gpll_usb480m_xin24m_p, 36, 6, - 2, 0, 6, 19, 9, 0), - RK_COMPOSITE(CLK_CAM1_OUT, "clk_cam1_out", gpll_usb480m_xin24m_p, 36, - 14, 2, 8, 6, 19, 10, 0), - RK_COMPNODIV(ACLK_VO, "aclk_vo", gpll300_cpll250_gpll100_xin24m_p, 37, - 0, 2, 20, 0, 0), - RK_COMPNOMUX(HCLK_VO, "hclk_vo", "aclk_vo", 37, 8, 4, 20, 1, 0), - RK_COMPNOMUX(PCLK_VO, "pclk_vo", "aclk_vo", 37, 12, 4, 20, 2, 0), - RK_COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", cpll_gpll_hpll_vpll_p, 38, 6, - 2, 0, 5, 20, 6, 0), - RK_COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, 39, 10, 2, - 0, 8, 20, 10, 0), - RK_COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, 40, 10, 2, - 0, 8, 20, 11, 0), - RK_COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, 41, 10, 2, - 0, 8, 20, 12, 0), - RK_COMPNODIV(CLK_EDP_200M, "clk_edp_200m", gpll200_gpll150_cpll125_p, - 38, 8, 2, 21, 9, 0), - RK_COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", gpll_cpll_p, 42, 7, 1, 0, 5, - 22, 0, 0), - RK_COMPNOMUX(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 42, 8, 4, 22, - 1, 0), - RK_COMPNODIV(ACLK_RGA_PRE, "aclk_rga_pre", - gpll300_cpll250_gpll100_xin24m_p, 43, 0, 2, 23, 0, 0), - RK_COMPNOMUX(HCLK_RGA_PRE, "hclk_rga_pre", "aclk_rga_pre", 43, 8, 4, 23, - 1, 0), - RK_COMPNOMUX(PCLK_RGA_PRE, "pclk_rga_pre", "aclk_rga_pre", 43, 12, 4, - 22, 12, 0), - RK_COMPNODIV(CLK_RGA_CORE, "clk_rga_core", gpll300_gpll200_gpll100_p, - 43, 2, 2, 23, 6, 0), - RK_COMPNODIV(CLK_IEP_CORE, "clk_iep_core", gpll300_gpll200_gpll100_p, - 43, 4, 2, 23, 9, 0), - RK_COMPNODIV(DCLK_EBC, "dclk_ebc", gpll400_cpll333_gpll200_p, 43, 6, 2, - 23, 11, 0), - RK_COMPOSITE(ACLK_RKVENC_PRE, "aclk_rkvenc_pre", gpll_cpll_npll_p, 44, - 6, 2, 0, 5, 24, 0, 0), - RK_COMPNOMUX(HCLK_RKVENC_PRE, "hclk_rkvenc_pre", "aclk_rkvenc_pre", 44, - 8, 4, 24, 1, 0), - RK_COMPOSITE(CLK_RKVENC_CORE, "clk_rkvenc_core", gpll_cpll_npll_vpll_p, - 45, 14, 2, 0, 5, 24, 8, 0), - RK_COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", aclk_rkvdec_pre_p, 47, - 7, 1, 0, 5, 25, 0, 0), - RK_COMPNOMUX(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 47, - 8, 4, 25, 1, 0), - RK_COMPOSITE(CLK_RKVDEC_CA, "clk_rkvdec_ca", gpll_cpll_npll_vpll_p, 48, - 6, 2, 0, 5, 25, 6, 0), - RK_COMPOSITE(CLK_RKVDEC_CORE, "clk_rkvdec_core", clk_rkvdec_core_p, 49, - 14, 2, 8, 5, 25, 7, 0), - RK_COMPOSITE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", - gpll_cpll_npll_vpll_p, 49, 6, 2, 0, 5, 25, 8, 0), - RK_COMPNODIV(ACLK_BUS, "aclk_bus", gpll200_gpll150_gpll100_xin24m_p, 50, - 0, 2, 26, 0, 0), - RK_COMPNODIV(PCLK_BUS, "pclk_bus", gpll100_gpll75_cpll50_xin24m_p, 50, - 4, 2, 26, 1, 0), - RK_COMPOSITE(CLK_TSADC_TSEN, "clk_tsadc_tsen", xin24m_gpll100_cpll100_p, - 51, 4, 2, 0, 3, 26, 5, 0), - RK_COMPNOMUX(CLK_TSADC, "clk_tsadc", "clk_tsadc_tsen", 51, 8, 7, 26, - 6, 0), - RK_COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_usb480m_p, 52, 8, - 2, 0, 7, 27, 13, 0), - RK_FRACTION(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", 53, 27, - 14, 0), - RK_MUX(0, "sclk_uart1_mux", sclk_uart1_p, 52, 12, 2, 0), - RK_COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_usb480m_p, 54, 8, - 2, 0, 7, 28, 1, 0), - RK_FRACTION(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", 55, 28, - 2, 0), - RK_MUX(0, "sclk_uart2_mux", sclk_uart2_p, 54, 12, 2, 0), - RK_COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_usb480m_p, 56, 8, - 2, 0, 7, 28, 5, 0), - RK_FRACTION(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", 57, 28, - 6, 0), - RK_MUX(0, "sclk_uart3_mux", sclk_uart3_p, 56, 12, 2, 0), - RK_COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_usb480m_p, 58, 8, - 2, 0, 7, 28, 9, 0), - RK_FRACTION(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", 59, 28, - 10, 0), - RK_MUX(0, "sclk_uart4_mux", sclk_uart4_p, 58, 12, 2, 0), - RK_COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_usb480m_p, 60, 8, - 2, 0, 7, 28, 13, 0), - RK_FRACTION(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", 61, 28, - 14, 0), - RK_MUX(0, "sclk_uart5_mux", sclk_uart5_p, 60, 12, 2, 0), - RK_COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_usb480m_p, 62, 8, - 2, 0, 7, 29, 1, 0), - RK_FRACTION(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", 63, 29, - 2, 0), - RK_MUX(0, "sclk_uart6_mux", sclk_uart6_p, 62, 12, 2, 0), - RK_COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_usb480m_p, 64, 8, - 2, 0, 7, 29, 5, 0), - RK_FRACTION(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", 65, 29, - 6, 0), - RK_MUX(0, "sclk_uart7_mux", sclk_uart7_p, 64, 12, 2, 0), - RK_COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_usb480m_p, 66, 8, - 2, 0, 7, 29, 9, 0), - RK_FRACTION(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", 67, 29, - 10, 0), - RK_MUX(0, "sclk_uart8_mux", sclk_uart8_p, 66, 12, 2, 0), - RK_COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_usb480m_p, 68, 8, - 2, 0, 7, 29, 13, 0), - RK_FRACTION(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", 69, 29, - 14, 0), - RK_MUX(0, "sclk_uart9_mux", sclk_uart9_p, 68, 12, 2, 0), - RK_COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 70, 7, 1, 0, 5, 27, - 6, 0), - RK_COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 70, 15, 1, 8, 5, 27, - 8, 0), - RK_COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 71, 7, 1, 0, 5, 27, - 10, 0), - RK_COMPNODIV(CLK_I2C, "clk_i2c", clk_i2c_p, 71, 8, 2, 32, 10, 0), - RK_COMPNODIV(CLK_SPI0, "clk_spi0", gpll200_xin24m_cpll100_p, 72, 0, 1, - 30, 11, 0), - RK_COMPNODIV(CLK_SPI1, "clk_spi1", gpll200_xin24m_cpll100_p, 72, 2, 1, - 30, 13, 0), - RK_COMPNODIV(CLK_SPI2, "clk_spi2", gpll200_xin24m_cpll100_p, 72, 4, 1, - 30, 15, 0), - RK_COMPNODIV(CLK_SPI3, "clk_spi3", gpll200_xin24m_cpll100_p, 72, 6, 1, - 31, 1, 0), - RK_COMPNODIV(CLK_PWM1, "clk_pwm1", gpll100_xin24m_cpll100_p, 72, 8, 1, - 31, 11, 0), - RK_COMPNODIV(CLK_PWM2, "clk_pwm2", gpll100_xin24m_cpll100_p, 72, 10, 1, - 31, 14, 0), - RK_COMPNODIV(CLK_PWM3, "clk_pwm3", gpll100_xin24m_cpll100_p, 72, 12, 1, - 32, 1, 0), - RK_COMPNODIV(DBCLK_GPIO, "dbclk_gpio", xin24m_32k_p, 72, 14, 1, 32, - 11, 0), - RK_COMPNODIV(ACLK_TOP_HIGH, "aclk_top_high", - cpll500_gpll400_gpll300_xin24m_p, 73, 0, 2, 33, 0, 0), - RK_COMPNODIV(ACLK_TOP_LOW, "aclk_top_low", - gpll400_gpll300_gpll200_xin24m_p, 73, 4, 2, 33, 1, 0), - RK_COMPNODIV(HCLK_TOP, "hclk_top", gpll150_gpll100_gpll75_xin24m_p, 73, - 8, 2, 33, 2, 0), - RK_COMPNODIV(PCLK_TOP, "pclk_top", gpll100_gpll75_cpll50_xin24m_p, 73, - 12, 2, 33, 3, 0), - RK_COMPNODIV(CLK_OPTC_ARB, "clk_optc_arb", xin24m_cpll100_p, 73, 15, 1, - 33, 9, 0), + + /* CRU_CLKSEL_CON00 */ + /* 0:4 clk_core0_div DIV */ + /* 5 Reserved */ + /* 6 clk_core_i_sel MUX */ + /* 7 clk_core_ndft_sel MUX */ + /* 8:12 clk_core1_div DIV */ + /* 13:14 Reserved */ + /* 15 clk_core_ndft_mux_sel MUX */ + + /* CRU_CLKSEL_CON01 */ + /* 0:4 clk_core2_div DIV */ + /* 5:7 Reserved */ + /* 8:12 clk_core3_div DIV */ + /* 13:15 Reserved */ + + /* CRU_CLKSEL_CON02 */ + COMP(0, "sclk_core_src_c", apll_gpll_npll_p, 0, 2, 0, 4, 8, 2), + /* 4:7 Reserved */ + /* 10:14 Reserved */ + MUX(0, "sclk_core_pre_sel", sclk_core_pre_p, 0, 2, 15, 1), + + /* CRU_CLKSEL_CON03 */ + CDIV(0, "atclk_core_div", "armclk", 0, 3, 0, 5), + /* 5:7 Reserved */ + CDIV(0, "gicclk_core_div", "armclk", 0, 3, 8, 5), + /* 13:15 Reserved */ + + /* CRU_CLKSEL_CON04 */ + CDIV(0, "pclk_core_pre_div", "armclk", 0, 4, 0, 5), + /* 5:7 Reserved */ + CDIV(0, "periphclk_core_pre_div", "armclk", 0, 4, 8, 5), + /* 13:15 Reserved */ + + /* CRU_CLKSEL_CON05 */ + /* 0:7 Reserved */ + /* 8:12 aclk_core_ndft_div DIV */ + /* 13 Reserved */ + /* 14:15 aclk_core_biu2bus_sel MUX */ + + /* CRU_CLKSEL_CON06 */ + COMP(0, "clk_gpu_pre_c", mpll_gpll_cpll_npll_p, 0, 6, 0, 4, 6, 2), + /* 4:5 Reserved */ + CDIV(0, "aclk_gpu_pre_div", "clk_gpu_pre_c", 0, 6, 8, 2), + /* 10 Reserved */ + MUX(CLK_GPU_PRE_MUX, "clk_gpu_pre_mux_sel", clk_gpu_pre_mux_p, 0, 6, 11, 1), + CDIV(0, "pclk_gpu_pre_div", "clk_gpu_pre_c", 0, 6, 12, 4), + + /* CRU_CLKSEL_CON07 */ + COMP(0, "clk_npu_src_c", npll_gpll_p, 0, 7, 0, 4, 6, 1), + COMP(0, "clk_npu_np5_c", npll_gpll_p, 0, 7, 4, 2, 7, 1), + MUX(CLK_NPU_PRE_NDFT, "clk_npu_pre_ndft", clk_npu_pre_ndft_p, 0, 7, + 8, 1), + /* 9:14 Reserved */ + MUX(CLK_NPU, "clk_npu", clk_npu_p, 0, 7, 15, 1), + + /* CRU_CLKSEL_CON08 */ + CDIV(0, "hclk_npu_pre_div", "clk_npu", 0, 8, 0, 4), + CDIV(0, "pclk_npu_pre_div", "clk_npu", 0, 8, 4, 4), + /* 8:15 Reserved */ + + /* CRU_CLKSEL_CON09 */ + COMP(0, "clk_ddrphy1x_src_c", dpll_gpll_cpll_p, 0, 9, 0, 5, 6, 2), + /* 5 Reserved */ + /* 8:14 Reserved */ + MUX(CLK_DDR1X, "clk_ddr1x", clk_ddr1x_p, RK_CLK_COMPOSITE_GRF, 9, + 15, 1), + + /* CRU_CLKSEL_CON10 */ + CDIV(0, "clk_msch_div", "clk_ddr1x", 0, 10, 0, 2), + MUX(0, "aclk_perimid_sel", gpll300_gpll200_gpll100_xin24m_p, 0, 10, 4, 2), + MUX(0, "hclk_perimid_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 10, 6, 2), + MUX(0, "aclk_gic_audio_sel", gpll200_gpll150_gpll100_xin24m_p, 0, 10, 8, 2), + MUX(0, "hclk_gic_audio_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 10, 10, 2), + MUX(0, "dclk_sdmmc_buffer_sel", gpll100_gpll75_gpll50_p, 0, 10, 12, 2), + /* 14:15 Reserved */ + + /* CRU_CLKSEL_CON11 */ + COMP(0, "clk_i2s0_8ch_tx_src_c", gpll_cpll_npll_p, 0, 11, 0, 7, 8, 2), + /* 7 Reserved */ + MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, 0, 11, 10, + 2), + /* 12:14 Reserved */ + MUX(0, "i2s0_mclkout_tx_sel", i2s0_mclkout_tx_p, 0, 11, 15, 1), + + /* CRU_CLKSEL_CON12 */ + FRACT(0, "clk_i2s0_8ch_tx_frac_div", "clk_i2s0_8ch_tx_src", 0, 12), + + /* CRU_CLKSEL_CON13 */ + COMP(0, "clk_i2s0_8ch_rx_src_c", gpll_cpll_npll_p, 0, 13, 0, 7, 8, 2), + /* 7 Reserved */ + MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, 0, 13, 10, + 2), + /* 12:14 Reserved */ + MUX(0, "i2s0_mclkout_rx_sel", i2s0_mclkout_rx_p, 0, 13, 15, 1), + + /* CRU_CLKSEL_CON14 */ + FRACT(0, "clk_i2s0_8ch_rx_frac_div", "clk_i2s0_8ch_rx_src", 0, 14), + + /* CRU_CLKSEL_CON15 */ + COMP(0, "clk_i2s1_8ch_tx_src_c", gpll_cpll_npll_p, 0, 15, 0, 7, 8, 2), + /* 7 Reserved */ + MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, 0, 15, 10, + 2), + /* 12:14 Reserved */ + MUX(0, "i2s1_mclkout_tx_sel", i2s1_mclkout_tx_p, 0, 11, 15, 1), + + /* CRU_CLKSEL_CON16 */ + FRACT(0, "clk_i2s1_8ch_tx_frac_div", "clk_i2s1_8ch_tx_src", 0, 16), + + /* CRU_CLKSEL_CON17 */ + COMP(0, "clk_i2s1_8ch_rx_src_c", gpll_cpll_npll_p, 0, 17, 0, 7, 8, 2), + /* 7 Reserved */ + MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, 0, 17, 10, + 2), + /* 12:14 Reserved */ + MUX(0, "i2s1_mclkout_rx_sel", i2s1_mclkout_rx_p, 0, 17, 15, 1), + + /* CRU_CLKSEL_CON18 */ + FRACT(0, "clk_i2s1_8ch_rx_frac_div", "clk_i2s1_8ch_rx_src", 0, 18), + + /* CRU_CLKSEL_CON19 */ + COMP(0, "clk_i2s2_2ch_src_c", gpll_cpll_npll_p, 0, 19, 0, 7, 8, 2), + /* 7 Reserved */ + MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, 0, 19, 10, + 2), + /* 12:14 Reserved */ + MUX(0, "i2s2_mclkout_sel", i2s2_mclkout_p, 0, 19, 15, 1), + + /* CRU_CLKSEL_CON20 */ + FRACT(0, "clk_i2s2_2ch_frac_div", "clk_i2s2_2ch_src", 0, 20), + + /* CRU_CLKSEL_CON21 */ + COMP(0, "clk_i2s3_2ch_tx_src_c", gpll_cpll_npll_p, 0, 21, 0, 7, 8, 2), + /* 7 Reserved */ + MUX(CLK_I2S3_2CH_TX, "clk_i2s3_2ch_tx", clk_i2s3_2ch_tx_p, 0, 21, 10, + 2), + /* 12:14 Reserved */ + MUX(0, "i2s3_mclkout_tx_sel", i2s3_mclkout_tx_p, 0, 21, 15, 1), + + /* CRU_CLKSEL_CON22 */ + FRACT(0, "clk_i2s3_2ch_tx_frac_div", "clk_i2s3_2ch_tx_src", 0, 22), + + /* CRU_CLKSEL_CON23 */ + COMP(0, "mclk_spdif_8ch_src_c", cpll_gpll_p, 0, 23, 0, 7, 14, 1), + /* 7 Reserved */ + MUX(0, "mclk_pdm_sel", mclk_pdm_p, 0, 23, 8, 2), + MUX(0, "clk_acdcdig_i2c_sel", clk_i2c_p, 0, 23, 10, 2), + /* 12:13 Reserved */ + MUX(MCLK_SPDIF_8CH, "mclk_spdif_8ch", mclk_spdif_8ch_p, 0, 23, 15, + 1), + + /* CRU_CLKSEL_CON24 */ + FRACT(0, "mclk_spdif_8ch_frac_div", "mclk_spdif_8ch_src", 0, 24), + + /* CRU_CLKSEL_CON25 */ + COMP(0, "sclk_audpwm_src_c", gpll_cpll_p, 0, 25, 0, 5, 14, 1), + /* 6:13 Reserved */ + MUX(SCLK_AUDPWM, "sck_audpwm_sel", sclk_audpwm_p, 0, 25, 15, 1), + + /* CRU_CLKSEL_CON26 */ + FRACT(0, "sclk_audpwm_frac_frac", "sclk_audpwm_src", 0, 26), + + /* CRU_CLKSEL_CON27 */ + MUX(0, "aclk_secure_flash_sel", gpll200_gpll150_gpll100_xin24m_p, 0, 27, 0, 2), + MUX(0, "hclk_secure_flash_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 27, 2, 2), + MUX(0, "clk_crypto_ns_core_sel", gpll200_gpll150_gpll100_p, 0, 27, 4, 2), + MUX(0, "clk_crypto_ns_pka_sel", gpll300_gpll200_gpll100_p, 0, 27, 6, 2), + /* 8:15 Reserved */ + + /* CRU_CLKSEL_CON28 */ + MUX(0, "nclk_nandc_sel", clk_nandc_p, 0, 28, 0, 2), + /* 2:3 Reserved */ + MUX(0, "sclk_sfc_sel", sclk_sfc_p, 0, 28, 4, 3), + /* 7 Reserved */ + MUX(0, "bclk_emmc_sel", gpll200_gpll150_cpll125_p, 0, 28, 8, 2), + /* 10:11 Reserved */ + MUX(0, "cclk_emmc_sel", cclk_emmc_p, RK_CLK_MUX_REPARENT, 28, 12, 3), + /* 15 Reserved */ + + /* CRU_CLKSEL_CON29 */ + MUX(0, "aclk_pipe_sel", aclk_pipe_p, 0, 29, 0, 2), + /* 2:3 Reserved */ + CDIV(0, "pclk_pipe_div", "aclk_pipe", 0, 29, 4, 4), + MUX(0, "clk_usb3otg0_suspend_sel", xin24m_32k_p, 0, 29, 8, 1), + MUX(0, "clk_usb3otg1_suspend_sel", xin24m_32k_p, 0, 29, 9, 1), + /* 10:12 Reserved */ + MUX(0, "clk_xpcs_eee_sel", gpll200_cpll125_p, 0, 29, 13, 1), + /* 14:15 Reserved */ + + /* CRU_CLKSEL_CON30 */ + MUX(0, "aclk_php_sel", gpll300_gpll200_gpll100_xin24m_p, 0, 30, 0, 2), + MUX(0, "hclk_php_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 30, 2, 2), + CDIV(0, "pclk_php_div", "aclk_php", 0, 30, 4, 4), + MUX(0, "clk_sdmmc0_sel", clk_sdmmc_p, RK_CLK_MUX_REPARENT, 30, 8, 3), + /* 11 Reserved */ + MUX(0, "clk_sdmmc1_sel", clk_sdmmc_p, 0, 30, 12, 3), + /* 15 Reserved */ + + /* CRU_CLKSEL_CON31 */ + MUX(SCLK_GMAC0_RX_TX, "clk_gmac0_rx_tx", mux_gmac0_rx_tx_p, 0, 31, + 0, 2), + MUX(SCLK_GMAC0, "clk_gmac0", mux_gmac0_p, 0, 31, 2, 1), + MUX(SCLK_GMAC0_RMII_SPEED, "clk_gmac0_rmii_speed", + mux_gmac0_rmii_speed_p, 0, 31, 3, 1), + MUX(SCLK_GMAC0_RGMII_SPEED, "clk_gmac0_rgmii_speed", + mux_gmac0_rgmii_speed_p, RK_CLK_MUX_REPARENT, 31, 4, 2), + MUX(0, "clk_mac0_2top_sel", clk_mac_2top_p, 0, 31, 8, 2), + MUX(0, "clk_gmac0_ptp_ref_sel", clk_gmac_ptp_p, 0, 31, 12, 2), + MUX(0, "clk_mac0_out_sel", cpll125_cpll50_cpll25_xin24m_p, 0, 31, 14, 2), + + FFACT(0, "clk_gmac0_tx_div5", "clk_gmac0", 1, 5), + FFACT(0, "clk_gmac0_tx_div50", "clk_gmac0", 1, 50), + FFACT(0, "clk_gmac0_rx_div2", "clk_gmac0", 1, 2), + FFACT(0, "clk_gmac0_rx_div20", "clk_gmac0", 1, 20), + + /* CRU_CLKSEL_CON32 */ + MUX(0, "aclk_usb_sel", gpll300_gpll200_gpll100_xin24m_p, 0, 32, 0, 2), + MUX(0, "hclk_usb_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 32, 4, 2), + CDIV(0, "pclk_usb_div", "aclk_usb", 0, 32, 4, 4), + MUX(0, "clk_sdmmc2_sel", clk_sdmmc_p, 0, 32, 8, 3), + /* 11:15 Reserved */ + + /* CRU_CLKSEL_CON33 */ + MUX(SCLK_GMAC1_RX_TX, "clk_gmac1_rx_tx", mux_gmac1_rx_tx_p, 0, 33, + 0, 2), + MUX(SCLK_GMAC1, "clk_gmac1", mux_gmac1_p, 0, 33, 2, 1), + MUX(SCLK_GMAC1_RMII_SPEED, "clk_gmac1_rmii_speed", + mux_gmac1_rmii_speed_p, 0, 33, 3, 1), + MUX(SCLK_GMAC1_RGMII_SPEED, "clk_gmac1_rgmii_speed", + mux_gmac1_rgmii_speed_p, RK_CLK_MUX_REPARENT, 33, 4, 2), + /* 6:7 Reserved */ + MUX(0, "clk_mac1_2top_sel", clk_mac_2top_p, 0, 33, 8, 2), + MUX(0, "clk_gmac1_ptp_ref_sel", clk_gmac_ptp_p, 0, 33, 12, 2), + MUX(0, "clk_mac1_out_sel", cpll125_cpll50_cpll25_xin24m_p, 0, 33, 14, 2), + + FFACT(0, "clk_gmac1_tx_div5", "clk_gmac1", 1, 5), + FFACT(0, "clk_gmac1_tx_div50", "clk_gmac1", 1, 50), + FFACT(0, "clk_gmac1_rx_div2", "clk_gmac1", 1, 2), + FFACT(0, "clk_gmac1_rx_div20", "clk_gmac1", 1, 20), + + /* CRU_CLKSEL_CON34 */ + MUX(0, "aclk_vi_sel", gpll400_gpll300_gpll200_xin24m_p, 0, 34, 0, 2), + /* 2:3 Reserved */ + CDIV(0, "hclk_vi_div", "aclk_vi", 0, 34, 4, 4), + CDIV(0, "pclk_vi_div", "aclk_vi", 0, 34, 8, 4), + /* 12:13 Reserved */ + MUX(0, "dclk_vicap1_sel", cpll333_gpll300_gpll200_p, 0, 34, 14, 2), + + /* CRU_CLKSEL_CON35 */ + COMP(0, "clk_isp_c", cpll_gpll_hpll_p, 0, 35, 0, 5, 6, 2), + /* 5 Reserved */ + COMP(0, "clk_cif_out_c", gpll_usb480m_xin24m_p, 0, 35, 8, 6, 14, 2), + + /* CRU_CLKSEL_CON36 */ + COMP(0, "clk_cam0_out_c", gpll_usb480m_xin24m_p, 0, 36, 0, 6, 6, 2), + COMP(0, "clk_cam1_out_c", gpll_usb480m_xin24m_p, 0, 36, 8, 6, 14, 2), + + /* CRU_CLKSEL_CON37 */ + MUX(0, "aclk_vo_sel", gpll300_cpll250_gpll100_xin24m_p, 0, 37, 0, 2), + /* 2:7 Reserved */ + CDIV(0, "hclk_vo_div", "aclk_vo", 0, 37, 8, 4), + CDIV(0, "pclk_vo_div", "aclk_vo", 0, 37, 12, 4), + + /* CRU_CLKSEL_CON38 */ + COMP(0, "aclk_vop_pre_c", cpll_gpll_hpll_vpll_p, 0, 38, 0, 5, 6, 2), + /* 5 Reserved */ + MUX(0, "clk_edp_200m_sel", gpll200_gpll150_cpll125_p, 0, 38, 8, 2), + /* 10:15 Reserved */ + + /* CRU_CLKSEL_CON39 */ + COMP(0, "dclk_vop0_c", hpll_vpll_gpll_cpll_p, 0, 39, 0, 8, 10, 2), + /* 12:15 Reserved */ + + /* CRU_CLKSEL_CON40 */ + COMP(0, "dclk_vop1_c", hpll_vpll_gpll_cpll_p, 0, 40, 0, 8, 10, 2), + /* 12:15 Reserved */ + + /* CRU_CLKSEL_CON41 */ + COMP(0, "dclk_vop2_c", hpll_vpll_gpll_cpll_p, 0, 41, 0, 8, 10, 2), + /* 12:15 Reserved */ + + /* CRU_CLKSEL_CON42 */ + COMP(0, "aclk_vpu_pre_c", gpll_cpll_p, 0, 42, 0, 5, 7, 1), + /* 5:6 Reserved */ + CDIV(0, "hclk_vpu_pre_div", "aclk_vpu_pre", 0, 42, 8, 4), + /* 12:15 Reserved */ + + /* CRU_CLKSEL_CON43 */ + MUX(0, "aclk_rga_pre_sel", gpll300_cpll250_gpll100_xin24m_p, 0, 43, 0, 2), + MUX(0, "clk_rga_core_sel", gpll300_gpll200_gpll100_p, 0, 43, 2, 2), + MUX(0, "clk_iep_core_sel", gpll300_gpll200_gpll100_p, 0, 43, 4, 2), + MUX(0, "dclk_ebc_sel", gpll400_cpll333_gpll200_p, 0, 43, 6, 2), + CDIV(0, "hclk_rga_pre_div", "aclk_rga_pre", 0, 43, 8, 4), + CDIV(0, "pclk_rga_pre_div", "aclk_rga_pre", 0, 43, 12, 4), + + /* CRU_CLKSEL_CON44 */ + COMP(0, "aclk_rkvenc_pre_c", gpll_cpll_npll_p, 0, 44, 0, 5, 6, 2), + /* 5 Reserved */ + CDIV(0, "hclk_rkvenc_pre_div", "aclk_rkvenc_pre", 0, 44, 8, 4), + /* 12:15 Reserved */ + + /* CRU_CLKSEL_CON45 */ + COMP(0, "clk_rkvenc_core_c", gpll_cpll_npll_vpll_p, 0, 45, 0, 5, 14, 2), + /* 5:13 Reserved */ + + /* CRU_CLKSEL_CON46 */ + + /* CRU_CLKSEL_CON47 */ + COMP(0, "aclk_rkvdec_pre_c", aclk_rkvdec_pre_p, 0, 47, 0, 5, 7, 1), + /* 5:6 Reserved */ + CDIV(0, "hclk_rkvdec_pre_div", "aclk_rkvdec_pre", 0, 47, 8, 4), + /* 12:15 Reserved */ + + /* CRU_CLKSEL_CON48 */ + COMP(0, "clk_rkvdec_ca_c", gpll_cpll_npll_vpll_p, 0, 48, 0, 5, 6, 2), + /* 5 Reserved */ + /* 8:15 Reserved */ + + /* CRU_CLKSEL_CON49 */ + COMP(0, "clk_rkvdec_hevc_ca_c", gpll_cpll_npll_vpll_p, 0, 49, 0, 5, 6, 2), + /* 5 Reserved */ + COMP(0, "clk_rkvdec_core_c", clk_rkvdec_core_p, 0, 49, 8, 5, 14, 2), + /* 13 Reserved */ + + /* CRU_CLKSEL_CON50 */ + MUX(0, "aclk_bus_sel", gpll200_gpll150_gpll100_xin24m_p, 0, 50, 0, 2), + /* 2:3 Reserved */ + MUX(0, "pclk_bus_sel", gpll100_gpll75_cpll50_xin24m_p, 0, 50, 4, 2), + /* 6:15 Reserved */ + + /* CRU_CLKSEL_CON51 */ + COMP(0, "clk_tsadc_tsen_c", xin24m_gpll100_cpll100_p, 0, 51, 0, 3, 4, 2), + /* 6:7 Reserved */ + CDIV(0, "clk_tsadc_div", "clk_tsadc_tsen", 0, 51, 8, 7), + /* 15 Reserved */ + + /* CRU_CLKSEL_CON52 */ + COMP(0, "clk_uart1_src_c", gpll_cpll_usb480m_p, 0, 52, 0, 7, 8, 2), + /* 7 Reserved */ + /* 10:11 Reserved */ + MUX(0, "sclk_uart1_sel", sclk_uart1_p, 0, 52, 12, 2), + + /* CRU_CLKSEL_CON53 */ + FRACT(0, "clk_uart1_frac_frac", "clk_uart1_src", 0, 53), + + /* CRU_CLKSEL_CON54 */ + COMP(0, "clk_uart2_src_c", gpll_cpll_usb480m_p, 0, 54, 0, 7, 8, 2), + /* 7 Reserved */ + /* 10:11 Reserved */ + MUX(0, "sclk_uart2_sel", sclk_uart2_p, 0, 52, 12, 2), + + /* CRU_CLKSEL_CON55 */ + FRACT(0, "clk_uart2_frac_frac", "clk_uart2_src", 0, 55), + + /* CRU_CLKSEL_CON56 */ + COMP(0, "clk_uart3_src_c", gpll_cpll_usb480m_p, 0, 54, 0, 7, 8, 2), + /* 7 Reserved */ + /* 10:11 Reserved */ + MUX(0, "sclk_uart3_sel", sclk_uart3_p, 0, 56, 12, 2), + + /* CRU_CLKSEL_CON57 */ + FRACT(0, "clk_uart3_frac_frac", "clk_uart3_src", 0, 57), + + /* CRU_CLKSEL_CON58 */ + COMP(0, "clk_uart4_src_c", gpll_cpll_usb480m_p, 0, 58, 0, 7, 8, 2), + /* 7 Reserved */ + /* 10:11 Reserved */ + MUX(0, "sclk_uart4_sel", sclk_uart4_p, 0, 58, 12, 2), + + /* CRU_CLKSEL_CON59 */ + FRACT(0, "clk_uart4_frac_frac", "clk_uart4_src", 0, 59), + + /* CRU_CLKSEL_CON60 */ + COMP(0, "clk_uart5_src_c", gpll_cpll_usb480m_p, 0, 60, 0, 7, 8, 2), + /* 7 Reserved */ + /* 10:11 Reserved */ + MUX(0, "sclk_uart5_sel", sclk_uart5_p, 0, 60, 12, 2), + + /* CRU_CLKSEL_CON61 */ + FRACT(0, "clk_uart5_frac_frac", "clk_uart5_src", 0, 61), + + /* CRU_CLKSEL_CON62 */ + COMP(0, "clk_uart6_src_c", gpll_cpll_usb480m_p, 0, 62, 0, 7, 8, 2), + /* 7 Reserved */ + /* 10:11 Reserved */ + MUX(0, "sclk_uart6_sel", sclk_uart6_p, 0, 62, 12, 2), + + /* CRU_CLKSEL_CON63 */ + FRACT(0, "clk_uart6_frac_frac", "clk_uart6_src", 0, 63), + + /* CRU_CLKSEL_CON64 */ + COMP(0, "clk_uart7_src_c", gpll_cpll_usb480m_p, 0, 64, 0, 7, 8, 2), + /* 7 Reserved */ + /* 10:11 Reserved */ + MUX(0, "sclk_uart7_sel", sclk_uart7_p, 0, 64, 12, 2), + + /* CRU_CLKSEL_CON65 */ + FRACT(0, "clk_uart7_frac_frac", "clk_uart7_src", 0, 65), + + /* CRU_CLKSEL_CON66 */ + COMP(0, "clk_uart8_src_c", gpll_cpll_usb480m_p, 0, 66, 0, 7, 8, 2), + /* 7 Reserved */ + /* 10:11 Reserved */ + MUX(0, "sclk_uart8_sel", sclk_uart8_p, 0, 66, 12, 2), + + /* CRU_CLKSEL_CON67 */ + FRACT(0, "clk_uart8_frac_frac", "clk_uart8_src", 0, 67), + + /* CRU_CLKSEL_CON68 */ + COMP(0, "clk_uart9_src_c", gpll_cpll_usb480m_p, 0, 68, 0, 7, 8, 2), + /* 7 Reserved */ + /* 10:11 Reserved */ + MUX(0, "sclk_uart9_sel", sclk_uart9_p, 0, 68, 12, 2), + + /* CRU_CLKSEL_CON69 */ + FRACT(0, "clk_uart9_frac_frac", "clk_uart9_src", 0, 69), + + /* CRU_CLKSEL_CON70 */ + COMP(0, "clk_can0_c", gpll_cpll_p, 0, 70, 0, 5, 7, 1), + /* 5:6 Reserved */ + COMP(0, "clk_can1_c", gpll_cpll_p, 0, 70, 8, 5, 15, 1), + /* 13:14 Reserved */ + + /* CRU_CLKSEL_CON71 */ + COMP(0, "clk_can2_c", gpll_cpll_p, 0, 71, 0, 5, 7, 1), + /* 5:6 Reserved */ + MUX(0, "clk_i2c_sel", clk_i2c_p, 0, 71, 8, 2), + /* 10:15 Reserved */ + + /* CRU_CLKSEL_CON72 */ + MUX(0, "clk_spi0_sel", gpll200_xin24m_cpll100_p, 0, 72, 0, 2), + MUX(0, "clk_spi1_sel", gpll200_xin24m_cpll100_p, 0, 72, 2, 2), + MUX(0, "clk_spi2_sel", gpll200_xin24m_cpll100_p, 0, 72, 4, 2), + MUX(0, "clk_spi3_sel", gpll200_xin24m_cpll100_p, 0, 72, 6, 2), + MUX(0, "clk_pwm1_sel", gpll100_xin24m_cpll100_p, 0, 72, 8, 2), + MUX(0, "clk_pwm2_sel", gpll100_xin24m_cpll100_p, 0, 72, 10, 2), + MUX(0, "clk_pwm3_sel", gpll100_xin24m_cpll100_p, 0, 72, 12, 2), + MUX(0, "dbclk_gpio_sel", xin24m_32k_p, 0, 72, 14, 1), + /* 15 Reserved */ + + /* CRU_CLKSEL_CON73 */ + MUX(0, "aclk_top_high_sel", cpll500_gpll400_gpll300_xin24m_p, 0, 73, 0, 2), + /* 2:3 Reserved */ + MUX(0, "aclk_top_low_sel", gpll400_gpll300_gpll200_xin24m_p, 0, 73, 4, 2), + /* 6:7 Reserved */ + MUX(0, "hclk_top_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 73, 8, 2), + /* 10:11 Reserved */ + MUX(0, "pclk_top_sel", gpll100_gpll75_cpll50_xin24m_p, 0, 73, 12, 2), + /* 14 Reserved */ + MUX(0, "clk_optc_arb_sel", xin24m_cpll100_p, 0, 73, 15 , 1), + + /* CRU_CLKSEL_CON74 */ + /* 0:7 clk_testout_div CDIV */ + /* 8:12 clk_testout_sel MUX */ + + /* CRU_CLKSEL_CON75 */ + CDIV(0, "clk_gpll_div_400m_div", "gpll", 0, 75, 0, 5), + CDIV(0, "clk_gpll_div_300m_div", "gpll", 0, 75, 8, 5), + + /* CRU_CLKSEL_CON76 */ + CDIV(0, "clk_gpll_div_200m_div", "gpll", 0, 76, 0, 5), + CDIV(0, "clk_gpll_div_150m_div", "gpll", 0, 76, 8, 5), + + /* CRU_CLKSEL_CON77 */ + CDIV(0, "clk_gpll_div_100m_div", "gpll", 0, 77, 0, 5), + CDIV(0, "clk_gpll_div_75m_div", "gpll", 0, 77, 8, 5), + + /* CRU_CLKSEL_CON78 */ + CDIV(0, "clk_gpll_div_20m_div", "gpll", 0, 78, 0, 6), + CDIV(0, "clk_cpll_div_500m_div", "cpll", 0, 78, 8, 5), + + /* CRU_CLKSEL_CON79 */ + CDIV(0, "clk_cpll_div_333m_div", "cpll", 0, 79, 0, 6), + CDIV(0, "clk_cpll_div_250m_div", "cpll", 0, 79, 8, 5), + + /* CRU_CLKSEL_CON80 */ + CDIV(0, "clk_cpll_div_125m_div", "cpll", 0, 80, 0, 6), + CDIV(0, "clk_cpll_div_62P5m_div", "cpll", 0, 80, 8, 5), + + /* CRU_CLKSEL_CON81 */ + CDIV(0, "clk_cpll_div_50m_div", "cpll", 0, 81, 0, 5), + CDIV(0, "clk_cpll_div_25m_div", "cpll", 0, 81, 8, 6), + + /* CRU_CLKSEL_CON82 */ + CDIV(0, "clk_cpll_div_100m_div", "cpll", 0, 82, 0, 5), + CDIV(0, "clk_osc0_div_750k_div", "xin24m", 0, 82, 8, 6), + + /* CRU_CLKSEL_CON83 */ + CDIV(0, "clk_i2s3_2ch_rx_src_div", "clk_i2s3_2ch_rx_src_sel", 0, 83, 0, 7), + /* 7 Reserved */ + MUX(0, "clk_i2s3_2ch_rx_src_sel", gpll_cpll_npll_p, 0, 83, 8, 2), + MUX(CLK_I2S3_2CH_RX, "clk_i2s3_2ch_rx", clk_i2s3_2ch_rx_p, 0, 83, 10, + 2), + /* 12:14 Reserved */ + MUX(0, "i2s3_mclkout_rx_sel", i2s3_mclkout_rx_p, 0, 83, 15, 1), + + /* CRU_CLKSEL_CON84 */ + FRACT(0, "clk_i2s3_2ch_rx_frac_div", "clk_i2s3_2ch_rx_src", 0, 84), }; /* GATES */ static struct rk_cru_gate rk3568_gates[] = { - RK_GATE(CLK_CORE_PVTM, "clk_core_pvtm", "xin24m", 1, 10), - RK_GATE(CLK_CORE_PVTM_CORE, "clk_core_pvtm_core", "armclk", 1, 11), - RK_GATE(CLK_CORE_PVTPLL, "clk_core_pvtpll", "armclk", 1, 12), - RK_GATE(PCLK_CORE_PVTM, "pclk_core_pvtm", "pclk_core_pre", 1, 9), - RK_GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre_mux", 2, 3), - RK_GATE(PCLK_GPU_PVTM, "pclk_gpu_pvtm", "pclk_gpu_pre", 2, 6), - RK_GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 2, 7), - RK_GATE(CLK_GPU_PVTM_CORE, "clk_gpu_pvtm_core", "clk_gpu_src", 2, 8), - RK_GATE(CLK_GPU_PVTPLL, "clk_gpu_pvtpll", "clk_gpu_src", 2, 9), - RK_GATE(ACLK_NPU_PRE, "aclk_npu_pre", "clk_npu", 3, 4), - RK_GATE(ACLK_NPU, "aclk_npu", "aclk_npu_pre", 3, 7), - RK_GATE(HCLK_NPU, "hclk_npu", "hclk_npu_pre", 3, 8), - RK_GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_pre", 3, 9), - RK_GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 3, 10), - RK_GATE(CLK_NPU_PVTM_CORE, "clk_npu_pvtm_core", "clk_npu_pre_ndft", - 3, 11), - RK_GATE(CLK_NPU_PVTPLL, "clk_npu_pvtpll", "clk_npu_pre_ndft", 3, 12), - RK_GATE(CLK24_DDRMON, "clk24_ddrmon", "xin24m", 4, 15), - RK_GATE(HCLK_SDMMC_BUFFER, "hclk_sdmmc_buffer", "hclk_gic_audio", 5, 8), - RK_GATE(ACLK_GIC600, "aclk_gic600", "aclk_gic_audio", 5, 4), - RK_GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_gic_audio", 5, 7), - RK_GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_gic_audio", 5, 10), - RK_GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_gic_audio", 5, 11), - RK_GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_gic_audio", 5, 12), - RK_GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_gic_audio", 5, 13), - RK_GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 6, 2), - RK_GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 6, 6), - RK_GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 6, 10), - RK_GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 6, 14), - RK_GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 7, 2), - RK_GATE(MCLK_I2S3_2CH_TX, "mclk_i2s3_2ch_tx", "clk_i2s3_2ch_tx", 7, 6), - RK_GATE(MCLK_I2S3_2CH_RX, "mclk_i2s3_2ch_rx", "clk_i2s3_2ch_rx", 7, 10), - RK_GATE(HCLK_PDM, "hclk_pdm", "hclk_gic_audio", 5, 14), - RK_GATE(HCLK_VAD, "hclk_vad", "hclk_gic_audio", 7, 12), - RK_GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_gic_audio", 7, 13), - RK_GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_gic_audio", 8, 0), - RK_GATE(HCLK_ACDCDIG, "hclk_acdcdig", "hclk_gic_audio", 8, 3), - RK_GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s3_2ch_tx", 8, 5), - RK_GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s3_2ch_rx", 8, 6), - RK_GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_secure_flash", 8, 11), - RK_GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_secure_flash", 8, 12), - RK_GATE(CLK_CRYPTO_NS_RNG, "clk_crypto_ns_rng", "hclk_secure_flash", - 8, 15), - RK_GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_secure_flash", 9, 10), - RK_GATE(CLK_TRNG_NS, "clk_trng_ns", "hclk_secure_flash", 9, 11), - RK_GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "hclk_secure_flash", 26, 9), - RK_GATE(CLK_OTPC_NS_SBPI, "clk_otpc_ns_sbpi", "xin24m", 26, 10), - RK_GATE(CLK_OTPC_NS_USR, "clk_otpc_ns_usr", "xin_osc0_half", 26, 11), - RK_GATE(HCLK_NANDC, "hclk_nandc", "hclk_secure_flash", 9, 0), - RK_GATE(HCLK_SFC, "hclk_sfc", "hclk_secure_flash", 9, 2), - RK_GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_secure_flash", 9, 3), - RK_GATE(ACLK_EMMC, "aclk_emmc", "aclk_secure_flash", 9, 5), - RK_GATE(HCLK_EMMC, "hclk_emmc", "hclk_secure_flash", 9, 6), - RK_GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 9, 9), - RK_GATE(ACLK_PCIE20_MST, "aclk_pcie20_mst", "aclk_pipe", 12, 0), - RK_GATE(ACLK_PCIE20_SLV, "aclk_pcie20_slv", "aclk_pipe", 12, 1), - RK_GATE(ACLK_PCIE20_DBI, "aclk_pcie20_dbi", "aclk_pipe", 12, 2), - RK_GATE(PCLK_PCIE20, "pclk_pcie20", "pclk_pipe", 12, 3), - RK_GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 12, 4), - RK_GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 12, 8), - RK_GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 12, 9), - RK_GATE(ACLK_PCIE30X1_DBI, "aclk_pcie30x1_dbi", "aclk_pipe", 12, 10), - RK_GATE(PCLK_PCIE30X1, "pclk_pcie30x1", "pclk_pipe", 12, 11), - RK_GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", - 12, 12), - RK_GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 13, 0), - RK_GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 13, 1), - RK_GATE(ACLK_PCIE30X2_DBI, "aclk_pcie30x2_dbi", "aclk_pipe", 13, 2), - RK_GATE(PCLK_PCIE30X2, "pclk_pcie30x2", "pclk_pipe", 13, 3), - RK_GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", - 13, 4), - RK_GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 11, 0), - RK_GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "gpll_20m", 11, 1), - RK_GATE(CLK_SATA0_RXOOB, "clk_sata0_rxoob", "cpll_50m", 11, 2), - RK_GATE(ACLK_SATA1, "aclk_sata1", "aclk_pipe", 11, 4), - RK_GATE(CLK_SATA1_PMALIVE, "clk_sata1_pmalive", "gpll_20m", 11, 5), - RK_GATE(CLK_SATA1_RXOOB, "clk_sata1_rxoob", "cpll_50m", 11, 6), - RK_GATE(ACLK_SATA2, "aclk_sata2", "aclk_pipe", 11, 8), - RK_GATE(CLK_SATA2_PMALIVE, "clk_sata2_pmalive", "gpll_20m", 11, 9), - RK_GATE(CLK_SATA2_RXOOB, "clk_sata2_rxoob", "cpll_50m", 11, 10), - RK_GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_pipe", 10, 8), - RK_GATE(CLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 10, 9), - RK_GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_pipe", 10, 12), - RK_GATE(CLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 10, 13), - RK_GATE(PCLK_XPCS, "pclk_xpcs", "pclk_pipe", 13, 6), - RK_GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_php", 15, 0), - RK_GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_php", 15, 2), - RK_GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_php", 15, 5), - RK_GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php", 15, 6), - RK_GATE(CLK_MAC0_REFOUT, "clk_mac0_refout", "clk_mac0_2top", 15, 12), - RK_GATE(HCLK_USB2HOST0, "hclk_usb2host0", "hclk_usb", 16, 12), - RK_GATE(HCLK_USB2HOST0_ARB, "hclk_usb2host0_arb", "hclk_usb", 16, 13), - RK_GATE(HCLK_USB2HOST1, "hclk_usb2host1", "hclk_usb", 16, 14), - RK_GATE(HCLK_USB2HOST1_ARB, "hclk_usb2host1_arb", "hclk_usb", 16, 15), - RK_GATE(HCLK_SDMMC2, "hclk_sdmmc2", "hclk_usb", 17, 0), - RK_GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_usb", 17, 3), - RK_GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_usb", 17, 4), - RK_GATE(CLK_MAC1_REFOUT, "clk_mac1_refout", "clk_mac1_2top", 17, 10), - RK_GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi", 18, 9), - RK_GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi", 18, 10), - RK_GATE(ACLK_ISP, "aclk_isp", "aclk_vi", 19, 0), - RK_GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 19, 1), - RK_GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "pclk_vi", 19, 4), - RK_GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 20, 8), - RK_GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 20, 9), - RK_GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 20, 13), - RK_GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo", 21, 0), - RK_GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo", 21, 1), - RK_GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo", 21, 2), - RK_GATE(PCLK_HDMI_HOST, "pclk_hdmi_host", "pclk_vo", 21, 3), - RK_GATE(CLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 21, 4), - RK_GATE(CLK_HDMI_CEC, "clk_hdmi_cec", "clk_rtc_32k", 21, 5), - RK_GATE(PCLK_DSITX_0, "pclk_dsitx_0", "pclk_vo", 21, 6), - RK_GATE(PCLK_DSITX_1, "pclk_dsitx_1", "pclk_vo", 21, 7), - RK_GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_vo", 21, 8), - RK_GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 22, 4), - RK_GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 22, 5), - RK_GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 23, 4), - RK_GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 23, 5), - RK_GATE(ACLK_IEP, "aclk_iep", "aclk_rga_pre", 23, 7), - RK_GATE(HCLK_IEP, "hclk_iep", "hclk_rga_pre", 23, 8), - RK_GATE(HCLK_EBC, "hclk_ebc", "hclk_rga_pre", 23, 10), - RK_GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_pre", 23, 12), - RK_GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre", 23, 13), - RK_GATE(ACLK_JENC, "aclk_jenc", "aclk_rga_pre", 23, 14), - RK_GATE(HCLK_JENC, "hclk_jenc", "hclk_rga_pre", 23, 15), - RK_GATE(PCLK_EINK, "pclk_eink", "pclk_rga_pre", 22, 14), - RK_GATE(HCLK_EINK, "hclk_eink", "hclk_rga_pre", 22, 15), - RK_GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 24, 6), - RK_GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 24, 7), - RK_GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 25, 4), - RK_GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 25, 5), - RK_GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 26, 4), - RK_GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 26, 7), - RK_GATE(CLK_SARADC, "clk_saradc", "xin24m", 26, 8), - RK_GATE(PCLK_SCR, "pclk_scr", "pclk_bus", 26, 12), - RK_GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus", 26, 13), - RK_GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 26, 14), - RK_GATE(ACLK_MCU, "aclk_mcu", "aclk_bus", 32, 13), - RK_GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus", 32, 14), - RK_GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 32, 15), - RK_GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 27, 12), - RK_GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 27, 15), - RK_GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 28, 0), - RK_GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_mux", 28, 3), - RK_GATE(PCLK_UART3, "pclk_uart3", "pclk_bus", 28, 4), - RK_GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 28, 7), - RK_GATE(PCLK_UART4, "pclk_uart4", "pclk_bus", 28, 8), - RK_GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 28, 11), - RK_GATE(PCLK_UART5, "pclk_uart5", "pclk_bus", 28, 12), - RK_GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 28, 15), - RK_GATE(PCLK_UART6, "pclk_uart6", "pclk_bus", 29, 0), - RK_GATE(SCLK_UART6, "sclk_uart6", "sclk_uart6_mux", 29, 3), - RK_GATE(PCLK_UART7, "pclk_uart7", "pclk_bus", 29, 4), - RK_GATE(SCLK_UART7, "sclk_uart7", "sclk_uart7_mux", 29, 7), - RK_GATE(PCLK_UART8, "pclk_uart8", "pclk_bus", 29, 8), - RK_GATE(SCLK_UART8, "sclk_uart8", "sclk_uart8_mux", 29, 11), - RK_GATE(PCLK_UART9, "pclk_uart9", "pclk_bus", 29, 12), - RK_GATE(SCLK_UART9, "sclk_uart9", "sclk_uart9_mux", 29, 15), - RK_GATE(PCLK_CAN0, "pclk_can0", "pclk_bus", 27, 5), - RK_GATE(PCLK_CAN1, "pclk_can1", "pclk_bus", 27, 7), - RK_GATE(PCLK_CAN2, "pclk_can2", "pclk_bus", 27, 9), - RK_GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 30, 0), - RK_GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 30, 1), - RK_GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 30, 2), - RK_GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 30, 3), - RK_GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 30, 4), - RK_GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 30, 5), - RK_GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus", 30, 6), - RK_GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 30, 7), - RK_GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus", 30, 8), - RK_GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 30, 9), - RK_GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 30, 10), - RK_GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 30, 12), - RK_GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 30, 14), - RK_GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus", 31, 0), - RK_GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 31, 10), - RK_GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 31, 12), - RK_GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", 31, 13), - RK_GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 31, 15), - RK_GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus", 32, 0), - RK_GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 32, 2), - RK_GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 31, 2), - RK_GATE(DBCLK_GPIO1, "dbclk_gpio1", "dbclk_gpio", 31, 3), - RK_GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 31, 4), - RK_GATE(DBCLK_GPIO2, "dbclk_gpio2", "dbclk_gpio", 31, 5), - RK_GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 31, 6), - RK_GATE(DBCLK_GPIO3, "dbclk_gpio3", "dbclk_gpio", 31, 7), - RK_GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus", 31, 8), - RK_GATE(DBCLK_GPIO4, "dbclk_gpio4", "dbclk_gpio", 31, 9), - RK_GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 32, 3), - RK_GATE(CLK_TIMER0, "clk_timer0", "xin24m", 32, 4), - RK_GATE(CLK_TIMER1, "clk_timer1", "xin24m", 32, 5), - RK_GATE(CLK_TIMER2, "clk_timer2", "xin24m", 32, 6), - RK_GATE(CLK_TIMER3, "clk_timer3", "xin24m", 32, 7), - RK_GATE(CLK_TIMER4, "clk_timer4", "xin24m", 32, 8), - RK_GATE(CLK_TIMER5, "clk_timer5", "xin24m", 32, 9), - RK_GATE(PCLK_PCIE30PHY, "pclk_pcie30phy", "pclk_top", 33, 8), - RK_GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top", 33, 13), - RK_GATE(PCLK_MIPIDSIPHY0, "pclk_mipidsiphy0", "pclk_top", 33, 14), - RK_GATE(PCLK_MIPIDSIPHY1, "pclk_mipidsiphy1", "pclk_top", 33, 15), - RK_GATE(PCLK_PIPEPHY0, "pclk_pipephy0", "pclk_top", 34, 4), - RK_GATE(PCLK_PIPEPHY1, "pclk_pipephy1", "pclk_top", 34, 5), - RK_GATE(PCLK_PIPEPHY2, "pclk_pipephy2", "pclk_top", 34, 6), - RK_GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_top", 34, 11), - RK_GATE(CLK_CPU_BOOST, "clk_cpu_boost", "xin24m", 34, 12), - RK_GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_top", 34, 13), - RK_GATE(PCLK_EDPPHY_GRF, "pclk_edpphy_grf", "pclk_top", 34, 14), + /* CRU_CLKGATE_CON00 */ + /* 0 clk_core */ + /* 1 clk_core0 */ + /* 2 clk_core1 */ + /* 3 clk_core2 */ + /* 4 clk_core3 */ + GATE(0, "sclk_core_src", "sclk_core_src_c", 0, 5), + /* 6 clk_npll_core */ + /* 7 sclk_core */ + GATE(0, "atclk_core", "atclk_core_div", 0, 8), + GATE(0, "gicclk_core", "gicclk_core_div", 0, 9), + GATE(0, "pclk_core_pre", "pclk_core_pre_div", 0, 10), + GATE(0, "periphclk_core_pre", "periphclk_core_pre_div", 0, 11), + /* 12 pclk_core */ + /* 13 periphclk_core */ + /* 14 tsclk_core */ + /* 15 cntclk_core */ + + /* CRU_CLKGATE_CON01 */ + /* 0 aclk_core */ + /* 1 aclk_core_biuddr */ + /* 2 aclk_core_biu2bus */ + /* 3 pclk_dgb_biu */ + /* 4 pclk_dbg */ + /* 5 pclk_dbg_daplite */ + /* 6 aclk_adb400_core2gic */ + /* 7 aclk_adb400_gic2core */ + /* 8 pclk_core_grf */ + GATE(PCLK_CORE_PVTM, "pclk_core_pvtm", "pclk_core_pre", 1, 9), + GATE(CLK_CORE_PVTM, "clk_core_pvtm", "xin24m", 1, 10), + GATE(CLK_CORE_PVTM_CORE, "clk_core_pvtm_core", "armclk", 1, 11), + GATE(CLK_CORE_PVTPLL, "clk_core_pvtpll", "armclk", 1, 12), + /* 13 clk_core_div2 */ + /* 14 clk_apll_core */ + /* 15 clk_jtag */ + + /* CRU_CLKGATE_CON02 */ + /* 0 clk_gpu_src */ + GATE(CLK_GPU_SRC, "clk_gpu_src", "clk_gpu_pre_c", 2, 0), + /* 1 Reserved */ + GATE(PCLK_GPU_PRE, "pclk_gpu_pre", "pclk_gpu_pre_div", 2, 2), + GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre_c", 2, 3), + /* 4 aclk_gpu_biu */ + /* 5 pclk_gpu_biu */ + GATE(PCLK_GPU_PVTM, "pclk_gpu_pvtm", "pclk_gpu_pre", 2, 6), + GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 2, 7), + GATE(CLK_GPU_PVTM_CORE, "clk_gpu_pvtm_core", "clk_gpu_src", 2, 8), + GATE(CLK_GPU_PVTPLL, "clk_gpu_pvtpll", "clk_gpu_src", 2, 9), + /* 10 clk_gpu_div2 */ + GATE(ACLK_GPU_PRE, "aclk_gpu_pre", "aclk_gpu_pre_div", 2, 11), + /* 12:15 Reserved */ + + /* CRU_CLKGATE_CON03 */ + GATE(CLK_NPU_SRC, "clk_npu_src", "clk_npu_src_c", 3, 0), + GATE(CLK_NPU_NP5, "clk_npu_np5", "clk_npu_np5_c", 3, 1), + GATE(HCLK_NPU_PRE, "hclk_npu_pre", "hclk_npu_pre_div", 3, 2), + GATE(PCLK_NPU_PRE, "pclk_npu_pre", "pclk_npu_pre_div", 3, 3), + /* 4 aclk_npu_biu */ + GATE(ACLK_NPU_PRE, "aclk_npu_pre", "clk_npu", 3, 4), + /* 5 hclk_npu_biu */ + /* 6 pclk_npu_biu */ + GATE(ACLK_NPU, "aclk_npu", "aclk_npu_pre", 3, 7), + GATE(HCLK_NPU, "hclk_npu", "hclk_npu_pre", 3, 8), + GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_pre", 3, 9), + GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 3, 10), + GATE(CLK_NPU_PVTM_CORE, "clk_npu_pvtm_core", "clk_npu_pre_ndft",3, 11), + GATE(CLK_NPU_PVTPLL, "clk_npu_pvtpll", "clk_npu_pre_ndft", 3, 12), + /* 13 clk_npu_div2 */ + /* 14:15 Reserved */ + + /* CRU_CLKGATE_CON04 */ + GATE(CLK_DDRPHY1X_SRC, "clk_ddrphy1x_src", "clk_ddrphy1x_src_c", 4, 0), + /* 1 clk_dpll_ddr */ + GATE(CLK_MSCH, "clk_msch", "clk_msch_div", 4, 2), + /* 3 clk_hwffc_ctrl */ + /* 4 aclk_ddrscramble */ + /* 5 aclk_msch */ + /* 6 clk_ddr_alwayson */ + /* 7 Reserved */ + /* 8 aclk_ddrsplit */ + /* 9 clk_ddrdft_ctl */ + /* 10 Reserved */ + /* 11 aclk_dma2ddr */ + /* 12 Reserved */ + /* 13 clk_ddrmon */ + /* 14 Reserved */ + GATE(CLK24_DDRMON, "clk24_ddrmon", "xin24m", 4, 15), + + /* CRU_CLKGATE_CON05 */ + GATE(ACLK_GIC_AUDIO, "aclk_gic_audio", "aclk_gic_audio_sel", 5, 0), + GATE(HCLK_GIC_AUDIO, "hclk_gic_audio", "hclk_gic_audio_sel", 5, 1), + /* 2 aclk_gic_audio_biu */ + /* 3 hclk_gic_audio_biu */ + GATE(ACLK_GIC600, "aclk_gic600", "aclk_gic_audio", 5, 4), + /* 5 aclk_gicadb_core2gic */ + /* 6 aclk_gicadb_gic2core */ + GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_gic_audio", 5, 7), + GATE(HCLK_SDMMC_BUFFER, "hclk_sdmmc_buffer", "hclk_gic_audio", 5, 8), + GATE(DCLK_SDMMC_BUFFER, "dclk_sdmmc_buffer", "dclk_sdmmc_buffer_sel", 5, 9), + GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_gic_audio", 5, 10), + GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_gic_audio", 5, 11), + GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_gic_audio", 5, 12), + GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_gic_audio", 5, 13), + GATE(HCLK_PDM, "hclk_pdm", "hclk_gic_audio", 5, 14), + GATE(MCLK_PDM, "mclk_pdm", "mclk_pdm_sel", 5, 15), + + /* CRU_CLKGATE_CON06 */ + GATE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_src_c", 6, 0), + GATE(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_frac_div", 6, 1), + GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 6, 2), + GATE(I2S0_MCLKOUT_TX, "i2s0_mclkout_tx", "i2s0_mclkout_tx_sel", 6, 3), + GATE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_src_c", 6, 4), + GATE(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_frac_div", 6, 5), + GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 6, 6), + GATE(I2S0_MCLKOUT_RX, "i2s0_mclkout_rx", "i2s0_mclkout_rx_sel", 6, 7), + GATE(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_src_c", 6, 8), + GATE(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_frac_div", 6, 9), + GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 6, 10), + GATE(I2S1_MCLKOUT_TX, "i2s1_mclkout_tx", "i2s1_mclkout_tx_sel", 6, 11), + GATE(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_src_c", 6, 12), + GATE(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_frac_div", 6, 13), + GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 6, 14), + GATE(I2S1_MCLKOUT_RX, "i2s1_mclkout_rx", "i2s1_mclkout_rx_sel", 6, 15), + + /* CRU_CLKGATE_CON07 */ + GATE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", "clk_i2s2_2ch_src_c", 7, 0), + GATE(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_frac_div", 7, 1), + GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 7, 2), + GATE(I2S2_MCLKOUT, "i2s2_mclkout", "i2s2_mclkout_sel", 7, 3), + GATE(CLK_I2S3_2CH_TX, "clk_i2s3_2ch_tx_src", "clk_i2s3_2ch_tx_src_c", 7, 4), + GATE(CLK_I2S3_2CH_TX_FRAC, "clk_i2s3_2ch_tx_frac", "clk_i2s3_2ch_tx_frac_div", 7, 5), + GATE(MCLK_I2S3_2CH_TX, "mclk_i2s3_2ch_tx", "clk_i2s3_2ch_tx", 7, 6), + GATE(I2S3_MCLKOUT_TX, "i2s3_mclkout_tx", "i2s3_mclkout_tx_sel", 7, 7), + GATE(CLK_I2S3_2CH_RX, "clk_i2s3_2ch_rx_src", "clk_i2s3_2ch_rx_src_div", 7, 8), + GATE(CLK_I2S3_2CH_RX_FRAC, "clk_i2s3_2ch_rx_frac", "clk_i2s3_2ch_rx_frac_div", 7, 9), + GATE(MCLK_I2S3_2CH_RX, "mclk_i2s3_2ch_rx", "clk_i2s3_2ch_rx", 7, 10), + GATE(I2S3_MCLKOUT_RX, "i2s3_mclkout_rx", "i2s3_mclkout_rx_sel", 7, 11), + GATE(HCLK_VAD, "hclk_vad", "hclk_gic_audio", 7, 12), + GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_gic_audio", 7, 13), + GATE(MCLK_SPDIF_8CH_SRC, "mclk_spdif_8ch_src", "mclk_spdif_8ch_src_c", 7, 14), + GATE(MCLK_SPDIF_8CH_FRAC, "mclk_spdif_8ch_frac", "mclk_spdif_8ch_frac_div", 7, 15), + + /* CRU_CLKGATE_CON08 */ + GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_gic_audio", 8, 0), + GATE(SCLK_AUDPWM_SRC, "sclk_audpwm_src", "sclk_audpwm_src_c", 8, 1), + GATE(SCLK_AUDPWM_FRAC, "sclk_audpwm_frac", "sclk_audpwm_frac_frac", 8, 2), + GATE(HCLK_ACDCDIG, "hclk_acdcdig", "hclk_gic_audio", 8, 3), + GATE(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", "clk_acdcdig_i2c_sel", 8, 4), + GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s3_2ch_tx", 8, 5), + GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s3_2ch_rx", 8, 6), + GATE(ACLK_SECURE_FLASH, "aclk_secure_flash", "aclk_secure_flash_sel", 8, 7), + GATE(HCLK_SECURE_FLASH, "hclk_secure_flash", "hclk_secure_flash_sel", 8, 8), + /* 9 aclk_secure_flash_biu */ + /* 10 hclk_secure_flash_biu */ + GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_secure_flash", 8, 11), + GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_secure_flash", 8, 12), + GATE(CLK_CRYPTO_NS_CORE, "clk_crypto_ns_core", "clk_crypto_ns_core_sel", 8, 13), + GATE(CLK_CRYPTO_NS_PKA, "clk_crypto_ns_pka", "clk_crypto_ns_pka_sel", 8, 14), + GATE(CLK_CRYPTO_NS_RNG, "clk_crypto_ns_rng", "hclk_secure_flash", 8, 15), + + /* CRU_CLKGATE_CON09 */ + GATE(HCLK_NANDC, "hclk_nandc", "hclk_secure_flash", 9, 0), + GATE(NCLK_NANDC, "nclk_nandc", "nclk_nandc_sel", 9, 1), + GATE(HCLK_SFC, "hclk_sfc", "hclk_secure_flash", 9, 2), + GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_secure_flash", 9, 3), + GATE(SCLK_SFC, "sclk_sfc", "sclk_sfc_sel", 9, 4), + GATE(ACLK_EMMC, "aclk_emmc", "aclk_secure_flash", 9, 5), + GATE(HCLK_EMMC, "hclk_emmc", "hclk_secure_flash", 9, 6), + GATE(BCLK_EMMC, "bclk_emmc", "bclk_emmc_sel", 9, 7), + GATE(CCLK_EMMC, "cclk_emmc", "cclk_emmc_sel", 9, 8), + GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 9, 9), + GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_secure_flash", 9, 10), + GATE(CLK_TRNG_NS, "clk_trng_ns", "hclk_secure_flash", 9, 11), + /* 12:15 Reserved */ + + /* CRU_CLKGATE_CON10 */ + GATE(ACLK_PIPE, "aclk_pipe", "aclk_pipe_sel", 10, 0), + GATE(PCLK_PIPE, "pclk_pipe", "pclk_pipe_div", 10, 1), + /* 2 aclk_pipe_biu */ + /* 3 pclk_pipe_biu */ + GATE(CLK_XPCS_EEE, "clk_xpcs_eee", "clk_xpcs_eee_sel", 10, 4), + /* 5 clk_xpcs_rx_div10 */ + /* 6 clk_xpcs_tx_div10 */ + /* 7 pclk_pipe_grf */ + GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_pipe", 10, 8), + GATE(CLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 10, 9), + GATE(CLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", "clk_usb3otg0_suspend_sel", 10, 10), + /* 11 clk_usb3otg0_pipe */ + GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_pipe", 10, 12), + GATE(CLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 10, 13), + GATE(CLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", "clk_usb3otg1_suspend_sel", 10, 14), + /* 15 clk_usb3otg1_pipe */ + + /* CRU_CLKGATE_CON11 */ + GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 11, 0), + GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "clk_gpll_div_20m", 11, 1), + GATE(CLK_SATA0_RXOOB, "clk_sata0_rxoob", "clk_cpll_div_50m", 11, 2), + /* 3 clk_sata0_pipe */ + GATE(ACLK_SATA1, "aclk_sata1", "aclk_pipe", 11, 4), + GATE(CLK_SATA1_PMALIVE, "clk_sata1_pmalive", "clk_gpll_div_20m", 11, 5), + GATE(CLK_SATA1_RXOOB, "clk_sata1_rxoob", "clk_cpll_div_50m", 11, 6), + /* 7 clk_sata1_pipe */ + GATE(ACLK_SATA2, "aclk_sata2", "aclk_pipe", 11, 8), + GATE(CLK_SATA2_PMALIVE, "clk_sata2_pmalive", "clk_gpll_div_20m", 11, 9), + GATE(CLK_SATA2_RXOOB, "clk_sata2_rxoob", "clk_cpll_div_50m", 11, 10), + /* 11 clk_sata2_pipe */ + /* 12:15 Reserved */ + + /* CRU_CLKGATE_CON12 */ + GATE(ACLK_PCIE20_MST, "aclk_pcie20_mst", "aclk_pipe", 12, 0), + GATE(ACLK_PCIE20_SLV, "aclk_pcie20_slv", "aclk_pipe", 12, 1), + GATE(ACLK_PCIE20_DBI, "aclk_pcie20_dbi", "aclk_pipe", 12, 2), + GATE(PCLK_PCIE20, "pclk_pcie20", "pclk_pipe", 12, 3), + GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 12, 4), + /* 5 clk_pcie20_pipe */ + /* 6:7 Reserved */ + GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 12, 8), + GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 12, 9), + GATE(ACLK_PCIE30X1_DBI, "aclk_pcie30x1_dbi", "aclk_pipe", 12, 10), + GATE(PCLK_PCIE30X1, "pclk_pcie30x1", "pclk_pipe", 12, 11), + GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", 12, 12), + /* 13 clk_pcie30x1_pipe */ + /* 14:15 Reserved */ + + /* CRU_CLKGATE_CON13 */ + GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 13, 0), + GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 13, 1), + GATE(ACLK_PCIE30X2_DBI, "aclk_pcie30x2_dbi", "aclk_pipe", 13, 2), + GATE(PCLK_PCIE30X2, "pclk_pcie30x2", "pclk_pipe", 13, 3), + GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", 13, 4), + /* 5 clk_pcie30x2_pipe */ + GATE(PCLK_XPCS, "pclk_xpcs", "pclk_pipe", 13, 6), + /* 7 clk_xpcs_qsgmii_tx */ + /* 8 clk_xpcs_qsgmii_rx */ + /* 9 clk_xpcs_xgxs_tx */ + /* 10 Reserved */ + /* 11 clk_xpcs_xgxs_rx */ + /* 12 clk_xpcs_mii0_tx */ + /* 13 clk_xpcs_mii0_rx */ + /* 14 clk_xpcs_mii1_tx */ + /* 15 clk_xpcs_mii1_rx */ + + /* CRU_CLKGATE_CON14 */ + GATE(ACLK_PERIMID, "aclk_perimid", "aclk_perimid_sel", 14, 0), + GATE(HCLK_PERIMID, "hclk_perimid", "hclk_perimid_sel", 14, 1), + /* 2 aclk_perimid_biu */ + /* 3 hclk_perimid_biu */ + /* 4:7 Reserved */ + GATE(ACLK_PHP, "aclk_php", "aclk_php_sel", 14, 8), + GATE(HCLK_PHP, "hclk_php", "hclk_php_sel", 14, 9), + GATE(PCLK_PHP, "pclk_php", "pclk_php_div", 14, 10), + /* 11 aclk_php_biu */ + /* 12 hclk_php_biu */ + /* 13 pclk_php_biu */ + /* 14:15 Reserved */ + + /* CRU_CLKGATE_CON15 */ + GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_php", 15, 0), + GATE(CLK_SDMMC0, "clk_sdmmc0", "clk_sdmmc0_sel", 15, 1), + GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_php", 15, 2), + GATE(CLK_SDMMC1, "clk_sdmmc1", "clk_sdmmc1_sel", 15, 3), + GATE(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", "clk_gmac0_ptp_ref_sel", 15, 4), + GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_php", 15, 5), + GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php", 15, 6), + GATE(CLK_MAC0_2TOP, "clk_mac0_2top", "clk_mac0_2top_sel", 15, 7), + GATE(CLK_MAC0_OUT, "clk_mac0_out", "clk_mac0_out_sel", 15, 8), + /* 9:11 Reserved */ + GATE(CLK_MAC0_REFOUT, "clk_mac0_refout", "clk_mac0_2top", 15, 12), + /* 13:15 Reserved */ + + /* CRU_CLKGATE_CON16 */ + GATE(ACLK_USB, "aclk_usb", "aclk_usb_sel", 16, 0), + GATE(HCLK_USB, "hclk_usb", "hclk_usb_sel", 16, 1), + GATE(PCLK_USB, "pclk_usb", "pclk_usb_div", 16, 2), + /* 3 aclk_usb_biu */ + /* 4 hclk_usb_biu */ + /* 5 pclk_usb_biu */ + /* 6 pclk_usb_grf */ + /* 7:11 Reserved */ + GATE(HCLK_USB2HOST0, "hclk_usb2host0", "hclk_usb", 16, 12), + GATE(HCLK_USB2HOST0_ARB, "hclk_usb2host0_arb", "hclk_usb", 16, 13), + GATE(HCLK_USB2HOST1, "hclk_usb2host1", "hclk_usb", 16, 14), + GATE(HCLK_USB2HOST1_ARB, "hclk_usb2host1_arb", "hclk_usb", 16, 15), + + /* CRU_CLKGATE_CON17 */ + GATE(HCLK_SDMMC2, "hclk_sdmmc2", "hclk_usb", 17, 0), + GATE(CLK_SDMMC2, "clk_sdmmc2", "clk_sdmmc2_sel", 17, 1), + GATE(CLK_GMAC1_PTP_REF, "clK_gmac1_ptp_ref", "clk_gmac1_ptp_ref_sel", 17, 2), + GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_usb", 17, 3), + GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_usb", 17, 4), + GATE(CLK_MAC1_2TOP, "clk_mac1_2top", "clk_mac1_2top_sel", 17, 5), + GATE(CLK_MAC1_OUT, "clk_mac1_out", "clk_mac1_out_sel", 17, 6), + /* 7:9 Reserved */ + GATE(CLK_MAC1_REFOUT, "clk_mac1_refout", "clk_mac1_2top", 17, 10), + /* 11:15 Reserved */ + + /* CRU_CLKGATE_CON18 */ + GATE(ACLK_VI, "aclk_vi", "aclk_vi_sel", 18, 0), + GATE(HCLK_VI, "hclk_vi", "hclk_vi_div", 18, 1), + GATE(PCLK_VI, "pclk_vi", "pclk_vi_div", 18, 2), + /* 3 aclk_vi_biu */ + /* 4 hclk_vi_biu */ + /* 5 pclk_vi_biu */ + /* 6:8 Reserved */ + GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi", 18, 9), + GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi", 18, 10), + GATE(DCLK_VICAP, "dclk_vicap", "dclk_vicap1_sel", 18, 11), + /* 12:15 Reserved */ + + /* CRU_CLKGATE_CON19 */ + GATE(ACLK_ISP, "aclk_isp", "aclk_vi", 19, 0), + GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 19, 1), + GATE(CLK_ISP, "clk_isp", "clk_isp_c", 19, 2), + /* 3 Reserved */ + GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "pclk_vi", 19, 4), + /* 5:7 Reserved */ + GATE(CLK_CIF_OUT, "clk_cif_out", "clk_cif_out_c", 19, 8), + GATE(CLK_CAM0_OUT, "clk_cam0_out", "clk_cam0_out_c", 19, 9), + GATE(CLK_CAM1_OUT, "clk_cam1_out", "clk_cam1_out_c", 19, 9), + /* 11:15 Reserved */ + + /* CRU_CLKGATE_CON20 */ + /* 0 Reserved or aclk_vo ??? */ + GATE(ACLK_VO, "aclk_vo", "aclk_vo_sel", 20, 0), + GATE(HCLK_VO, "hclk_vo", "hclk_vo_div", 20, 1), + GATE(PCLK_VO, "pclk_vo", "pclk_vo_div", 20, 2), + /* 3 aclk_vo_biu */ + /* 4 hclk_vo_biu */ + /* 5 pclk_vo_biu */ + GATE(ACLK_VOP_PRE, "aclk_vop_pre", "aclk_vop_pre_c", 20, 6), + /* 7 aclk_vop_biu */ + GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 20, 8), + GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 20, 9), + GATE(DCLK_VOP0, "dclk_vop0", "dclk_vop0_c", 20, 10), + GATE(DCLK_VOP1, "dclk_vop1", "dclk_vop1_c", 20, 11), + GATE(DCLK_VOP2, "dclk_vop2", "dclk_vop2_c", 20, 12), + GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 20, 13), + /* 14:15 Reserved */ + + /* CRU_CLKGATE_CON21 */ + GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo", 21, 0), + GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo", 21, 1), + GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo", 21, 2), + GATE(PCLK_HDMI_HOST, "pclk_hdmi_host", "pclk_vo", 21, 3), + GATE(CLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 21, 4), + GATE(CLK_HDMI_CEC, "clk_hdmi_cec", "clk_rtc_32k", 21, 5), + GATE(PCLK_DSITX_0, "pclk_dsitx_0", "pclk_vo", 21, 6), + GATE(PCLK_DSITX_1, "pclk_dsitx_1", "pclk_vo", 21, 7), + GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_vo", 21, 8), + GATE(CLK_EDP_200M, "clk_edp_200m", "clk_edp_200m_sel", 21, 9), + /* 10:15 Reserved */ + + /* CRU_CLKGATE_CON22 */ + GATE(ACLK_VPU_PRE, "aclk_vpu_pre", "aclk_vpu_pre_c", 22, 0), + GATE(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre_c", 22, 1), + /* 2 aclk_vpu_biu */ + /* 3 hclk_vpu_biu */ + GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 22, 4), + GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 22, 5), + /* 6:11 Reserved */ + GATE(PCLK_RGA_PRE, "pclk_rga_pre", "pclk_rga_pre_div", 22, 12), + /* 13 pclk_rga_biu */ + GATE(PCLK_EINK, "pclk_eink", "pclk_rga_pre", 22, 14), + GATE(HCLK_EINK, "hclk_eink", "hclk_rga_pre", 22, 15), + + /* CRU_CLKGATE_CON23 */ + GATE(ACLK_RGA_PRE, "aclk_rga_pre", "aclk_rga_pre_sel", 23, 0), + GATE(HCLK_RGA_PRE, "hclk_rga_pre", "hclk_rga_pre_div", 23, 1), + /* 2 aclk_rga_biu */ + /* 3 hclk_rga_biu */ + GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 23, 4), + GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 23, 5), + GATE(CLK_RGA_CORE, "clk_rga_core", "clk_rga_core_sel", 23, 6), + GATE(ACLK_IEP, "aclk_iep", "aclk_rga_pre", 23, 7), + GATE(HCLK_IEP, "hclk_iep", "hclk_rga_pre", 23, 8), + GATE(CLK_IEP_CORE, "clk_iep_core", "clk_iep_core_sel", 23, 9), + GATE(HCLK_EBC, "hclk_ebc", "hclk_rga_pre", 23, 10), + GATE(DCLK_EBC, "dclk_ebc", "dclk_ebc_sel", 23, 11), + GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_pre", 23, 12), + GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre", 23, 13), + GATE(ACLK_JENC, "aclk_jenc", "aclk_rga_pre", 23, 14), + GATE(HCLK_JENC, "hclk_jenc", "hclk_rga_pre", 23, 15), + + /* CRU_CLKGATE_CON24 */ + GATE(ACLK_RKVENC_PRE, "aclk_rkvenc_pre", "aclk_rkvenc_pre_c", 24, 0), + GATE(HCLK_RKVENC_PRE, "hclk_rkvenc_pre", "hclk_rkvenc_pre_div", 24, 1), + /* 2 Reserved */ + /* 3 aclk_rkvenc_biu */ + /* 4 hclk_rkvenc_biu */ + /* 5 Reserved */ + GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 24, 6), + GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 24, 7), + GATE(CLK_RKVENC_CORE, "clk_rkvenc_core", "clk_rkvenc_core_c", 24, 8), + /* 9:15 Reserved */ + + /* CRU_CLKGATE_CON25 */ + GATE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", "aclk_rkvdec_pre_c", 25, 0), + GATE(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "hclk_rkvdec_pre_div", 25, 1), + /* 2 aclk_rkvdec_biu */ + /* 3 hclk_rkvdec_biu */ + GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 25, 4), + GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 25, 5), + GATE(CLK_RKVDEC_CA, "clk_rkvdec_ca", "clk_rkvdec_ca_c", 25, 6), + GATE(CLK_RKVDEC_CORE, "clk_rkvdec_core", "clk_rkvdec_core_c", 25, 7), + GATE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", "clk_rkvdec_hevc_ca_c", 25, 8), + /* 9:15 Reserved */ + + /* CRU_CLKGATE_CON26 */ + GATE(ACLK_BUS, "aclk_bus", "aclk_bus_sel", 26, 0), + GATE(PCLK_BUS, "pclk_bus", "pclk_bus_sel", 26, 1), + /* 2 aclk_bus_biu */ + /* 3 pclk_bus_biu */ + GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 26, 4), + GATE(CLK_TSADC_TSEN, "clk_tsadc_tsen", "clk_tsadc_tsen_c", 26, 5), + GATE(CLK_TSADC, "clk_tsadc", "clk_tsadc_div", 26, 6), + GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 26, 7), + GATE(CLK_SARADC, "clk_saradc", "xin24m", 26, 8), + GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "hclk_secure_flash", 26, 9), + GATE(CLK_OTPC_NS_SBPI, "clk_otpc_ns_sbpi", "xin24m", 26, 10), + GATE(CLK_OTPC_NS_USR, "clk_otpc_ns_usr", "xin_osc0_half", 26, 11), + GATE(PCLK_SCR, "pclk_scr", "pclk_bus", 26, 12), + GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus", 26, 13), + GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 26, 14), + /* 15 Reserved */ + + /* CRU_CLKGATE_CON27 */ + /* 0 pclk_grf */ + /* 1 pclk_grf_vccio12 */ + /* 2 pclk_grf_vccio34 */ + /* 3 pclk_grf_vccio567 */ + GATE(PCLK_CAN0, "pclk_can0", "pclk_bus", 27, 5), + GATE(CLK_CAN0, "clk_can0", "clk_can0_c", 27, 6), + GATE(PCLK_CAN1, "pclk_can1", "pclk_bus", 27, 7), + GATE(CLK_CAN1, "clk_can1", "clk_can1_c", 27, 8), + GATE(PCLK_CAN2, "pclk_can2", "pclk_bus", 27, 9), + GATE(CLK_CAN2, "clk_can2", "clk_can2_c", 27, 10), + /* 11 Reserved */ + GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 27, 12), + GATE(CLK_UART1_SRC, "clk_uart1_src", "clk_uart1_src_c", 27, 13), + GATE(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_frac_frac", 27, 14), + GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_sel", 27, 15), + + /* CRU_CLKGATE_CON28 */ + GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 28, 0), + GATE(CLK_UART2_SRC, "clk_uart2_src", "clk_uart2_src_c", 28, 1), + GATE(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_frac_frac", 28, 2), + GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_sel", 28, 3), + GATE(PCLK_UART3, "pclk_uart3", "pclk_bus", 28, 4), + GATE(CLK_UART3_SRC, "clk_uart3_src", "clk_uart3_src_c", 28, 5), + GATE(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_frac_frac", 28, 6), + GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_sel", 28, 7), + GATE(PCLK_UART4, "pclk_uart4", "pclk_bus", 28, 8), + GATE(CLK_UART4_SRC, "clk_uart4_src", "clk_uart4_src_c", 28, 9), + GATE(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_frac_frac", 28, 10), + GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_sel", 28, 11), + GATE(PCLK_UART5, "pclk_uart5", "pclk_bus", 28, 12), + GATE(CLK_UART5_SRC, "clk_uart5_src", "clk_uart5_src_c", 28, 13), + GATE(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_frac_frac", 28, 14), + GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_sel", 28, 15), + + /* CRU_CLKGATE_CON29 */ + GATE(PCLK_UART6, "pclk_uart6", "pclk_bus", 29, 0), + GATE(CLK_UART6_SRC, "clk_uart6_src", "clk_uart6_src_c", 29, 1), + GATE(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_frac_frac", 29, 2), + GATE(SCLK_UART6, "sclk_uart6", "sclk_uart6_sel", 29, 3), + GATE(PCLK_UART7, "pclk_uart7", "pclk_bus", 29, 4), + GATE(CLK_UART7_SRC, "clk_uart7_src", "clk_uart7_src_c", 29, 5), + GATE(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_frac_frac", 29, 6), + GATE(SCLK_UART7, "sclk_uart7", "sclk_uart7_sel", 29, 7), + GATE(PCLK_UART8, "pclk_uart8", "pclk_bus", 29, 8), + GATE(CLK_UART8_SRC, "clk_uart8_src", "clk_uart8_src_c", 29, 9), + GATE(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_frac_frac", 29, 10), + GATE(SCLK_UART8, "sclk_uart8", "sclk_uart8_sel", 29, 11), + GATE(PCLK_UART9, "pclk_uart9", "pclk_bus", 29, 12), + GATE(CLK_UART9_SRC, "clk_uart9_src", "clk_uart9_src_c", 29, 13), + GATE(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_frac_frac", 29, 14), + GATE(SCLK_UART9, "sclk_uart9", "sclk_uart9_sel", 29, 15), + + /* CRU_CLKGATE_CON30 */ + GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 30, 0), + GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 30, 1), + GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 30, 2), + GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 30, 3), + GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 30, 4), + GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 30, 5), + GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus", 30, 6), + GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 30, 7), + GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus", 30, 8), + GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 30, 9), + GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 30, 10), + GATE(CLK_SPI0, "clk_spi0", "clk_spi0_sel", 30, 11), + GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 30, 12), + GATE(CLK_SPI1, "clk_spi1", "clk_spi1_sel", 30, 13), + GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 30, 14), + GATE(CLK_SPI2, "clk_spi2", "clk_spi2_sel", 30, 15), + + /* CRU_CLKGATE_CON31 */ + GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus", 31, 0), + GATE(CLK_SPI3, "clk_spi3", "clk_spi3_sel", 31, 1), + GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 31, 2), + GATE(DBCLK_GPIO1, "dbclk_gpio1", "dbclk_gpio", 31, 3), + GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 31, 4), + GATE(DBCLK_GPIO2, "dbclk_gpio2", "dbclk_gpio", 31, 5), + GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 31, 6), + GATE(DBCLK_GPIO3, "dbclk_gpio3", "dbclk_gpio", 31, 7), + GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus", 31, 8), + GATE(DBCLK_GPIO4, "dbclk_gpio4", "dbclk_gpio", 31, 9), + GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 31, 10), + GATE(CLK_PWM1, "clk_pwm1", "clk_pwm1_sel", 31, 11), + GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 31, 12), + GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", 31, 13), + GATE(CLK_PWM2, "clk_pwm2", "clk_pwm2_sel", 31, 14), + GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 31, 15), + + /* CRU_CLKGATE_CON32 */ + GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus", 32, 0), + GATE(CLK_PWM3, "clk_pwm3", "clk_pwm3_sel", 32, 1), + GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 32, 2), + GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 32, 3), + GATE(CLK_TIMER0, "clk_timer0", "xin24m", 32, 4), + GATE(CLK_TIMER1, "clk_timer1", "xin24m", 32, 5), + GATE(CLK_TIMER2, "clk_timer2", "xin24m", 32, 6), + GATE(CLK_TIMER3, "clk_timer3", "xin24m", 32, 7), + GATE(CLK_TIMER4, "clk_timer4", "xin24m", 32, 8), + GATE(CLK_TIMER5, "clk_timer5", "xin24m", 32, 9), + GATE(CLK_I2C, "clk_i2c", "clk_i2c_sel", 32, 10), + GATE(DBCLK_GPIO, "dbclk_gpio", "dbclk_gpio_sel", 32, 11), + /* 12 clk_timer */ + GATE(ACLK_MCU, "aclk_mcu", "aclk_bus", 32, 13), + GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus", 32, 14), + GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 32, 15), + + /* CRU_CLKGATE_CON33 */ + GATE(ACLK_TOP_HIGH, "aclk_top_high", "aclk_top_high_sel", 33, 0), + GATE(ACLK_TOP_LOW, "aclk_top_low", "aclk_top_low_sel", 33, 1), + GATE(HCLK_TOP, "hclk_top", "hclk_top_sel", 33, 2), + GATE(PCLK_TOP, "pclk_top", "pclk_top_sel", 33, 3), + /* 4 aclk_top_high_biu */ + /* 5 aclk_top_low_biu */ + /* 6 hclk_top_biu */ + /* 7 pclk_top_biu */ + GATE(PCLK_PCIE30PHY, "pclk_pcie30phy", "pclk_top", 33, 8), + GATE(CLK_OPTC_ARB, "clk_optc_arb", "clk_optc_arb_sel", 33, 9), + /* 10:11 Reserved */ + /* 12 pclk_top_cru */ + GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top", 33, 13), + GATE(PCLK_MIPIDSIPHY0, "pclk_mipidsiphy0", "pclk_top", 33, 14), + GATE(PCLK_MIPIDSIPHY1, "pclk_mipidsiphy1", "pclk_top", 33, 15), + + /* CRU_CLKGATE_CON34 */ + /* 0 pclk_apb2asb_chip_left */ + /* 1 pclk_apb2asb_chip_bottom */ + /* 2 pclk_asb2apb_chip_left */ + /* 3 pclk_asb2apb_chip_bottom */ + GATE(PCLK_PIPEPHY0, "pclk_pipephy0", "pclk_top", 34, 4), + GATE(PCLK_PIPEPHY1, "pclk_pipephy1", "pclk_top", 34, 5), + GATE(PCLK_PIPEPHY2, "pclk_pipephy2", "pclk_top", 34, 6), + /* 7 pclk_usb2phy0_grf */ + /* 8 pclk_usb2phy1_grf */ + /* 9 pclk_ddrphy */ + /* 10 clk_ddrphy */ + GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_top", 34, 11), + GATE(CLK_CPU_BOOST, "clk_cpu_boost", "xin24m", 34, 12), + GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_top", 34, 13), + GATE(PCLK_EDPPHY_GRF, "pclk_edpphy_grf", "pclk_top", 34, 14), + /* 15 clk_testout */ + + /* CRU_CLKGATE_CON35 */ + GATE(0, "clk_gpll_div_400m", "clk_gpll_div_400m_div", 35, 0), + GATE(0, "clk_gpll_div_300m", "clk_gpll_div_300m_div", 35, 1), + GATE(0, "clk_gpll_div_200m", "clk_gpll_div_200m_div", 35, 2), + GATE(0, "clk_gpll_div_150m", "clk_gpll_div_150m_div", 35, 3), + GATE(0, "clk_gpll_div_100m", "clk_gpll_div_100m_div", 35, 4), + GATE(0, "clk_gpll_div_75m", "clk_gpll_div_75m_div", 35, 5), + GATE(0, "clk_gpll_div_20m", "clk_gpll_div_20m_div", 35, 6), + GATE(CPLL_500M, "clk_cpll_div_500m", "clk_cpll_div_500m_div", 35, 7), + GATE(CPLL_333M, "clk_cpll_div_333m", "clk_cpll_div_333m_div", 35, 8), + GATE(CPLL_250M, "clk_cpll_div_250m", "clk_cpll_div_250m_div", 35, 9), + GATE(CPLL_125M, "clk_cpll_div_125m", "clk_cpll_div_125m_div", 35, 10), + GATE(CPLL_100M, "clk_cpll_div_100m", "clk_cpll_div_100m_div", 35, 11), + GATE(CPLL_62P5M, "clk_cpll_div_62P5m", "clk_cpll_div_62P5m_div", 35, 12), + GATE(CPLL_50M, "clk_cpll_div_50m", "clk_cpll_div_50m_div", 35, 13), + GATE(CPLL_25M, "clk_cpll_div_25m", "clk_cpll_div_25m_div", 35, 14), + GATE(0, "clk_osc0_div_750k", "clk_osc0_div_750k_div", 35, 15), }; diff --git a/sys/arm64/rockchip/clk/rk_clk_composite.c b/sys/arm64/rockchip/clk/rk_clk_composite.c index a04b3aa2193c..dd946413f8a9 100644 --- a/sys/arm64/rockchip/clk/rk_clk_composite.c +++ b/sys/arm64/rockchip/clk/rk_clk_composite.c @@ -256,26 +256,31 @@ rk_clk_composite_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout, const char **p_names; uint64_t best, cur; uint32_t div, div_reg, best_div, best_div_reg, val; - int p_idx, best_parent; + int p_idx, best_parent, orig_p_idx, nparents, temp_idx; + orig_p_idx = clknode_get_parent_idx(clk); + nparents = clknode_get_parents_num(clk); sc = clknode_get_softc(clk); dprintf("Finding best parent/div for target freq of %ju\n", *fout); p_names = clknode_get_parent_names(clk); for (best_div = 0, best = 0, p_idx = 0; - p_idx != clknode_get_parents_num(clk); p_idx++) { - p_clk = clknode_find_by_name(p_names[p_idx]); + p_idx != nparents; p_idx++) { + temp_idx = (p_idx + orig_p_idx) % nparents; + p_clk = clknode_find_by_name(p_names[temp_idx]); clknode_get_freq(p_clk, &fparent); dprintf("Testing with parent %s (%d) at freq %ju\n", - clknode_get_name(p_clk), p_idx, fparent); + clknode_get_name(p_clk), temp_idx, fparent); div = rk_clk_composite_find_best(sc, fparent, *fout, &div_reg); cur = fparent / div; - if ((*fout - cur) < (*fout - best)) { + if (abs(*fout - cur) < abs(*fout - best)) { best = cur; best_div = div; best_div_reg = div_reg; - best_parent = p_idx; + best_parent = temp_idx; dprintf("Best parent so far %s (%d) with best freq at " "%ju\n", clknode_get_name(p_clk), p_idx, best); + if(*fout == cur) + break; } } @@ -295,7 +300,7 @@ rk_clk_composite_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout, return (0); } - p_idx = clknode_get_parent_idx(clk); + p_idx = orig_p_idx; if (p_idx != best_parent) { dprintf("Switching parent index from %d to %d\n", p_idx, best_parent); diff --git a/sys/arm64/rockchip/clk/rk_clk_mux.c b/sys/arm64/rockchip/clk/rk_clk_mux.c index 3a15ce82b3dc..5331a86ebe60 100644 --- a/sys/arm64/rockchip/clk/rk_clk_mux.c +++ b/sys/arm64/rockchip/clk/rk_clk_mux.c @@ -161,7 +161,7 @@ rk_clk_mux_set_mux(struct clknode *clk, int idx) return(0); } - +#define CLK_SET_NOTBUSY 0x00020000 static int rk_clk_mux_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout, int flags, int *stop) @@ -171,6 +171,7 @@ rk_clk_mux_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout, const char **p_names; int p_idx, best_parent; int rv; + uint64_t best = 0, target = *fout; sc = clknode_get_softc(clk); @@ -183,20 +184,23 @@ rk_clk_mux_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout, return (0); } - dprintf("Finding best parent for target freq of %ju\n", *fout); + dprintf("Finding best parent for target freq of %ju\n", target); p_names = clknode_get_parent_names(clk); for (p_idx = 0; p_idx != clknode_get_parents_num(clk); p_idx++) { p_clk = clknode_find_by_name(p_names[p_idx]); dprintf("Testing with parent %s (%d)\n", clknode_get_name(p_clk), p_idx); - rv = clknode_set_freq(p_clk, *fout, flags | CLK_SET_DRYRUN, 0); + rv = clknode_set_freq(p_clk, *fout, flags | CLK_SET_DRYRUN | CLK_SET_NOTBUSY, 0); dprintf("Testing with parent %s (%d) rv=%d\n", clknode_get_name(p_clk), p_idx, rv); - if (rv == 0) { + if (rv == 0 && (abs(target - *fout) < abs(target - best))) { best_parent = p_idx; + best = *fout; p_best_clk = p_clk; *stop = 1; + if(best == target) + break; } } diff --git a/sys/arm64/rockchip/rk_tsadc.c b/sys/arm64/rockchip/rk_tsadc.c index 0d0d5d130b7f..c44302fba871 100644 --- a/sys/arm64/rockchip/rk_tsadc.c +++ b/sys/arm64/rockchip/rk_tsadc.c @@ -484,6 +484,10 @@ tsadc_init_tsensor(struct tsadc_softc *sc, struct tsensor *sensor) WR4(sc, TSADC_INT_EN, val); /* Shutdown temperature */ + /* https://forums.freebsd.org/threads/running-freebsd-on-radxa-rock-3c-rk3566-board.89389/post-624890 */ + /* titus */ + /* val = tsadc_raw_to_temp(sc, sc->shutdown_temp); */ + val = tsadc_temp_to_raw(sc, sc->shutdown_temp); val = tsadc_raw_to_temp(sc, sc->shutdown_temp); WR4(sc, TSADC_COMP_SHUT(sensor->channel), val); val = RD4(sc, TSADC_AUTO_CON); diff --git a/sys/conf/newvers.sh b/sys/conf/newvers.sh index a2b89f3caca7..9d5a0a64fea8 100644 --- a/sys/conf/newvers.sh +++ b/sys/conf/newvers.sh @@ -269,8 +269,8 @@ if [ -n "$git_cmd" ] ; then git="${git_b}-${git}" fi if git_tree_modified; then - git="${git}-dirty" - modified=yes + #git="${git}-dirty" + #modified=yes fi git=" ${git}" fi diff --git a/sys/contrib/device-tree/include/dt-bindings/pinctrl/rockchip.h b/sys/contrib/device-tree/include/dt-bindings/pinctrl/rockchip.h index 5f291045e8fd..96d97d83d475 100644 --- a/sys/contrib/device-tree/include/dt-bindings/pinctrl/rockchip.h +++ b/sys/contrib/device-tree/include/dt-bindings/pinctrl/rockchip.h @@ -1,14 +1,30 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Header providing constants for Rockchip pinctrl bindings. * * Copyright (c) 2013 MundoReader S.L. * Author: Heiko Stuebner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_H__ #define __DT_BINDINGS_ROCKCHIP_PINCTRL_H__ +#define RK_GPIO0 0 +#define RK_GPIO1 1 +#define RK_GPIO2 2 +#define RK_GPIO3 3 +#define RK_GPIO4 4 +#define RK_GPIO6 6 + #define RK_PA0 0 #define RK_PA1 1 #define RK_PA2 2 @@ -43,5 +59,39 @@ #define RK_PD7 31 #define RK_FUNC_GPIO 0 +#define RK_FUNC_0 0 +#define RK_FUNC_1 1 +#define RK_FUNC_2 2 +#define RK_FUNC_3 3 +#define RK_FUNC_4 4 +#define RK_FUNC_5 5 +#define RK_FUNC_6 6 +#define RK_FUNC_7 7 +#define RK_FUNC_8 8 +#define RK_FUNC_9 9 +#define RK_FUNC_10 10 +#define RK_FUNC_11 11 +#define RK_FUNC_12 12 +#define RK_FUNC_13 13 +#define RK_FUNC_14 14 +#define RK_FUNC_15 15 + +//PCA953X +#define PCA_IO0_0 0 +#define PCA_IO0_1 1 +#define PCA_IO0_2 2 +#define PCA_IO0_3 3 +#define PCA_IO0_4 4 +#define PCA_IO0_5 5 +#define PCA_IO0_6 6 +#define PCA_IO0_7 7 +#define PCA_IO1_0 8 +#define PCA_IO1_1 9 +#define PCA_IO1_2 10 +#define PCA_IO1_3 11 +#define PCA_IO1_4 12 +#define PCA_IO1_5 13 +#define PCA_IO1_6 14 +#define PCA_IO1_7 15 #endif diff --git a/sys/contrib/device-tree/src/arm64/rockchip/rk3399-nanopi-r4s.dts b/sys/contrib/device-tree/src/arm64/rockchip/rk3399-nanopi-r4s.dts index fe5b52610010..75d802205b34 100644 --- a/sys/contrib/device-tree/src/arm64/rockchip/rk3399-nanopi-r4s.dts +++ b/sys/contrib/device-tree/src/arm64/rockchip/rk3399-nanopi-r4s.dts @@ -68,6 +68,11 @@ status = "disabled"; }; +&sdmmc { + /delete-property/ sd-uhs-sdr104; + cap-sd-highspeed; +}; + &i2c4 { status = "disabled"; }; diff --git a/sys/contrib/device-tree/src/arm64/rockchip/rk3568-nanopi-r5c.dts b/sys/contrib/device-tree/src/arm64/rockchip/rk3568-nanopi-r5c.dts index c718b8dbb9c6..158aea440027 100644 --- a/sys/contrib/device-tree/src/arm64/rockchip/rk3568-nanopi-r5c.dts +++ b/sys/contrib/device-tree/src/arm64/rockchip/rk3568-nanopi-r5c.dts @@ -110,3 +110,8 @@ }; }; }; + +&sfc { + status = "disabled"; +}; + diff --git a/sys/contrib/device-tree/src/arm64/rockchip/rk3568-nanopi-r5s.dts b/sys/contrib/device-tree/src/arm64/rockchip/rk3568-nanopi-r5s.dts index b6ad8328c7eb..ab1fb3a42123 100644 --- a/sys/contrib/device-tree/src/arm64/rockchip/rk3568-nanopi-r5s.dts +++ b/sys/contrib/device-tree/src/arm64/rockchip/rk3568-nanopi-r5s.dts @@ -17,6 +17,13 @@ ethernet0 = &gmac0; }; + gmac0_clkin: external-gmac0-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac0_clkin"; + #clock-cells = <0>; + }; + gpio-leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -52,6 +59,7 @@ }; &gmac0 { +#if 0 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; assigned-clock-rates = <0>, <125000000>; @@ -68,8 +76,30 @@ snps,reset-active-low; /* Reset time is 15ms, 50ms for rtl8211f */ snps,reset-delays-us = <0 15000 50000>; +#endif + phy-mode = "rgmii"; + phy-handle = <&rgmii_phy0>; + phy-supply = <&vcc_3v3>; + clock_in_out = "input"; + + snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 15000 50000>; + + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus + &gmac0_clkinout>; + tx_delay = <0x3c>; rx_delay = <0x2f>; + status = "okay"; }; diff --git a/sys/contrib/device-tree/src/arm64/rockchip/rk3568-nanopi-r5s.dtsi b/sys/contrib/device-tree/src/arm64/rockchip/rk3568-nanopi-r5s.dtsi index 58ba328ea782..8abc251d740c 100644 --- a/sys/contrib/device-tree/src/arm64/rockchip/rk3568-nanopi-r5s.dtsi +++ b/sys/contrib/device-tree/src/arm64/rockchip/rk3568-nanopi-r5s.dtsi @@ -70,7 +70,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; enable-active-high; - gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; startup-delay-us = <200000>; vin-supply = <&vcc5v0_sys>; }; @@ -146,18 +146,22 @@ &cpu0 { cpu-supply = <&vdd_cpu>; + clocks = <&cru ARMCLK>; }; &cpu1 { cpu-supply = <&vdd_cpu>; + clocks = <&cru ARMCLK>; }; &cpu2 { cpu-supply = <&vdd_cpu>; + clocks = <&cru ARMCLK>; }; &cpu3 { cpu-supply = <&vdd_cpu>; + clocks = <&cru ARMCLK>; }; &gpu { @@ -210,12 +214,17 @@ rk809: pmic@20 { compatible = "rockchip,rk809"; reg = <0x20>; + interrupt-parent = <&gpio0>; interrupts = ; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + pinctrl-names = "default"; pinctrl-0 = <&pmic_int>; rockchip,system-power-controller; + vcc1-supply = <&vcc3v3_sys>; vcc2-supply = <&vcc3v3_sys>; vcc3-supply = <&vcc3v3_sys>; @@ -490,6 +499,7 @@ bus-width = <8>; max-frequency = <200000000>; non-removable; + disable-wp; pinctrl-names = "default"; pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; status = "okay"; @@ -516,6 +526,17 @@ status = "okay"; }; +&sfc { + status = "okay"; + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <75000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + &uart2 { status = "okay"; }; diff --git a/sys/contrib/device-tree/src/arm64/rockchip/rk3568-radxa-cm3i.dtsi b/sys/contrib/device-tree/src/arm64/rockchip/rk3568-radxa-cm3i.dtsi index c50fbdd48680..d811b05407a4 100644 --- a/sys/contrib/device-tree/src/arm64/rockchip/rk3568-radxa-cm3i.dtsi +++ b/sys/contrib/device-tree/src/arm64/rockchip/rk3568-radxa-cm3i.dtsi @@ -94,20 +94,25 @@ &cpu0 { cpu-supply = <&vdd_cpu>; + clocks = <&cru ARMCLK>; }; &cpu1 { cpu-supply = <&vdd_cpu>; + clocks = <&cru ARMCLK>; }; &cpu2 { cpu-supply = <&vdd_cpu>; + clocks = <&cru ARMCLK>; }; &cpu3 { cpu-supply = <&vdd_cpu>; + clocks = <&cru ARMCLK>; }; +#if 0 &display_subsystem { status = "disabled"; }; @@ -116,6 +121,7 @@ mali-supply = <&vdd_gpu>; status = "okay"; }; +#endif &i2c0 { status = "okay"; @@ -142,9 +148,18 @@ reg = <0x20>; interrupt-parent = <&gpio0>; interrupts = ; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + // fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + pinctrl-names = "default"; pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; wakeup-source; @@ -385,6 +400,7 @@ bus-width = <8>; max-frequency = <200000000>; non-removable; + disable-wp; pinctrl-names = "default"; pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; vmmc-supply = <&vcc_3v3>; diff --git a/sys/contrib/device-tree/src/arm64/rockchip/rk3568-radxa-e25.dts b/sys/contrib/device-tree/src/arm64/rockchip/rk3568-radxa-e25.dts index 63c4bd873188..22894af1dcf3 100644 --- a/sys/contrib/device-tree/src/arm64/rockchip/rk3568-radxa-e25.dts +++ b/sys/contrib/device-tree/src/arm64/rockchip/rk3568-radxa-e25.dts @@ -8,6 +8,7 @@ compatible = "radxa,e25", "radxa,cm3i", "rockchip,rk3568"; aliases { + mmc0 = &sdhci; mmc1 = &sdmmc0; }; @@ -58,7 +59,9 @@ regulator-max-microvolt = <5000000>; vin-supply = <&vcc5v0_sys>; }; - +#if 1 +//Попытка заставить работать sata +//Не работает pcie vcc3v3_ngff: vcc3v3-ngff-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -70,7 +73,7 @@ regulator-max-microvolt = <3300000>; vin-supply = <&vcc5v0_sys>; }; - +#endif /* actually fed by vcc5v0_sys, dependent * on pi6c clock generator */ @@ -178,6 +181,12 @@ status = "okay"; }; +#if 1 +&sata1 { + status = "okay"; +}; +#endif + &sdmmc0 { bus-width = <4>; cap-sd-highspeed; @@ -187,6 +196,7 @@ pinctrl-names = "default"; pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>; sd-uhs-sdr104; + sd-uhs-sdr50; vmmc-supply = <&vcc3v3_sd>; vqmmc-supply = <&vccio_sd>; status = "okay"; @@ -226,3 +236,18 @@ phy-supply = <&vcc3v3_ngff>; status = "okay"; }; + +&wdt { + status = "okay"; +}; + +#if 0 +&otp { + status = "okay"; +}; + +&rng { + status = "okay"; +}; +#endif + diff --git a/sys/contrib/device-tree/src/arm64/rockchip/rk3568-rock-3a.dts b/sys/contrib/device-tree/src/arm64/rockchip/rk3568-rock-3a.dts index 917f5b2b8aab..b2e9c5dbbdb5 100644 --- a/sys/contrib/device-tree/src/arm64/rockchip/rk3568-rock-3a.dts +++ b/sys/contrib/device-tree/src/arm64/rockchip/rk3568-rock-3a.dts @@ -119,7 +119,7 @@ vcc3v3_pcie: vcc3v3-pcie-regulator { compatible = "regulator-fixed"; enable-active-high; - gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pcie_enable_h>; regulator-name = "vcc3v3_pcie"; @@ -756,6 +756,10 @@ status = "okay"; }; +&sfc { + status = "okay"; +}; + &tsadc { rockchip,hw-tshut-mode = <1>; rockchip,hw-tshut-polarity = <0>; diff --git a/sys/contrib/device-tree/src/arm64/rockchip/rk3568.dtsi b/sys/contrib/device-tree/src/arm64/rockchip/rk3568.dtsi index f1be76a54ceb..33e05704a9f5 100644 --- a/sys/contrib/device-tree/src/arm64/rockchip/rk3568.dtsi +++ b/sys/contrib/device-tree/src/arm64/rockchip/rk3568.dtsi @@ -64,7 +64,7 @@ compatible = "rockchip,rk3568-pcie"; #address-cells = <3>; #size-cells = <2>; - bus-range = <0x0 0xf>; + bus-range = <0x10 0x1f>; clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, <&cru CLK_PCIE30X1_AUX_NDFT>; @@ -87,7 +87,7 @@ num-ib-windows = <6>; num-ob-windows = <2>; max-link-speed = <3>; - msi-map = <0x0 &gic 0x1000 0x1000>; + msi-map = <0x1000 &its 0x1000 0x1000>; num-lanes = <1>; phys = <&pcie30phy>; phy-names = "pcie-phy"; @@ -97,7 +97,7 @@ <0x0 0xf2000000 0x0 0x00100000>; ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>, - <0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>; + <0x03000000 0x3 0x40000000 0x3 0x40000000 0x0 0x40000000>; reg-names = "dbi", "apb", "config"; resets = <&cru SRST_PCIE30X1_POWERUP>; reset-names = "pipe"; @@ -117,7 +117,7 @@ compatible = "rockchip,rk3568-pcie"; #address-cells = <3>; #size-cells = <2>; - bus-range = <0x0 0xf>; + bus-range = <0x20 0x2f>; clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, <&cru CLK_PCIE30X2_AUX_NDFT>; @@ -140,6 +140,7 @@ num-ib-windows = <6>; num-ob-windows = <2>; max-link-speed = <3>; + //msi-map = <0x2000 &its 0x2000 0x1000>; msi-map = <0x0 &gic 0x2000 0x1000>; num-lanes = <2>; phys = <&pcie30phy>; @@ -175,11 +176,13 @@ clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>, <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>, - <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>; + <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>, + <&cru PCLK_XPCS>; clock-names = "stmmaceth", "mac_clk_rx", "mac_clk_tx", "clk_mac_refout", "aclk_mac", "pclk_mac", - "clk_mac_speed", "ptp_ref"; + "clk_mac_speed", "ptp_ref", + "pclk_xpcs"; resets = <&cru SRST_A_GMAC0>; reset-names = "stmmaceth"; rockchip,grf = <&grf>; diff --git a/sys/contrib/device-tree/src/arm64/rockchip/rk356x.dtsi b/sys/contrib/device-tree/src/arm64/rockchip/rk356x.dtsi index 61680c7ac489..63ff746a9dd6 100644 --- a/sys/contrib/device-tree/src/arm64/rockchip/rk356x.dtsi +++ b/sys/contrib/device-tree/src/arm64/rockchip/rk356x.dtsi @@ -315,14 +315,21 @@ gic: interrupt-controller@fd400000 { compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ - <0x0 0xfd460000 0 0x80000>; /* GICR */ + <0x0 0xfd460000 0 0xc0000>; /* GICR */ interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - mbi-alias = <0x0 0xfd410000>; - mbi-ranges = <296 24>; - msi-controller; + its: interrupt-controller@fd440000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0xfd440000 0x0 0x20000>; + }; }; usb_host0_ehci: usb@fd800000 { @@ -369,6 +376,12 @@ status = "disabled"; }; + xpcs: syscon@fda00000 { + compatible = "rockchip,rk3568-xpcs", "syscon"; + reg = <0x0 0xfda00000 0x0 0x200000>; + status = "disabled"; + }; + pmugrf: syscon@fdc20000 { compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xfdc20000 0x0 0x10000>; diff --git a/sys/dev/eqos/if_eqos.c b/sys/dev/eqos/if_eqos.c index d969c019a9a5..73243e0bc1f0 100644 --- a/sys/dev/eqos/if_eqos.c +++ b/sys/dev/eqos/if_eqos.c @@ -105,7 +105,36 @@ static struct resource_spec eqos_spec[] = { }; static void eqos_tick(void *softc); +static void eqos_txintr(void *softc); +static void +eqos_enable_csum_offload(struct eqos_softc *sc) +{ + uint32_t reg; + + EQOS_ASSERT_LOCKED(sc); + reg = RD4(sc, GMAC_MAC_CONFIGURATION); + if ((if_getcapenable(sc->ifp) & IFCAP_RXCSUM) != 0) + reg |= GMAC_MAC_CONFIGURATION_IPC; + else + reg &= ~GMAC_MAC_CONFIGURATION_IPC; + WR4(sc, GMAC_MAC_CONFIGURATION, reg); +} + +static int +eqos_miibus_wait_idle(struct eqos_softc *sc) +{ + uint32_t addr; + int retry; + + for (retry = MII_BUSY_RETRY; retry > 0; retry--) { + addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS); + if (!(addr & GMAC_MAC_MDIO_ADDRESS_GB)) + break; + DELAY(10); + } + return (retry); +} static int eqos_miibus_readreg(device_t dev, int phy, int reg) @@ -114,7 +143,10 @@ eqos_miibus_readreg(device_t dev, int phy, int reg) uint32_t addr; int retry, val; - addr = sc->csr_clock_range | + addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS); + addr &= GMAC_MAC_MDIO_ADDRESS_SKAP | + GMAC_MAC_MDIO_ADDRESS_C45E; + addr |= sc->csr_clock_range | (phy << GMAC_MAC_MDIO_ADDRESS_PA_SHIFT) | (reg << GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) | GMAC_MAC_MDIO_ADDRESS_GOC_READ | GMAC_MAC_MDIO_ADDRESS_GB; @@ -122,22 +154,17 @@ eqos_miibus_readreg(device_t dev, int phy, int reg) DELAY(100); - for (retry = MII_BUSY_RETRY; retry > 0; retry--) { - addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS); - if (!(addr & GMAC_MAC_MDIO_ADDRESS_GB)) { - val = RD4(sc, GMAC_MAC_MDIO_DATA) & 0xFFFF; - break; - } - DELAY(10); - } + retry = eqos_miibus_wait_idle(sc); if (!retry) { device_printf(dev, "phy read timeout, phy=%d reg=%d\n", phy, reg); return (ETIMEDOUT); } + val = RD4(sc, GMAC_MAC_MDIO_DATA) & 0xFFFF; return (val); } + static int eqos_miibus_writereg(device_t dev, int phy, int reg, int val) { @@ -145,9 +172,20 @@ eqos_miibus_writereg(device_t dev, int phy, int reg, int val) uint32_t addr; int retry; + retry = eqos_miibus_wait_idle(sc); + + if(!retry) { + device_printf(dev, "phy@%d busy before write\n", phy); + return EBUSY; + } + WR4(sc, GMAC_MAC_MDIO_DATA, val); - addr = sc->csr_clock_range | + addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS); + addr &= GMAC_MAC_MDIO_ADDRESS_SKAP | + GMAC_MAC_MDIO_ADDRESS_C45E; + + addr |= sc->csr_clock_range | (phy << GMAC_MAC_MDIO_ADDRESS_PA_SHIFT) | (reg << GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) | GMAC_MAC_MDIO_ADDRESS_GOC_WRITE | GMAC_MAC_MDIO_ADDRESS_GB; @@ -155,12 +193,7 @@ eqos_miibus_writereg(device_t dev, int phy, int reg, int val) DELAY(100); - for (retry = MII_BUSY_RETRY; retry > 0; retry--) { - addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS); - if (!(addr & GMAC_MAC_MDIO_ADDRESS_GB)) - break; - DELAY(10); - } + retry = eqos_miibus_wait_idle(sc); if (!retry) { device_printf(dev, "phy write timeout, phy=%d reg=%d\n", phy, reg); @@ -176,8 +209,11 @@ eqos_miibus_statchg(device_t dev) struct mii_data *mii = device_get_softc(sc->miibus); uint32_t reg; - EQOS_ASSERT_LOCKED(sc); + if (mii == NULL || sc->ifp == NULL || + (if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) == 0) + return; + EQOS_ASSERT_LOCKED(sc); if (mii->mii_media_status & IFM_ACTIVE) sc->link_up = true; else @@ -216,8 +252,25 @@ eqos_miibus_statchg(device_t dev) WR4(sc, GMAC_MAC_CONFIGURATION, reg); + if (bootverbose) + device_printf(dev, "GMAC_CONFIG %x\n", reg); + IF_EQOS_SET_SPEED(dev, IFM_SUBTYPE(mii->mii_media_active)); + reg = RD4(sc, GMAC_MAC_Q0_TX_FLOW_CTRL); + reg = 0; + reg |= 0xFFFFU << GMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT; + reg |= GMAC_MAC_Q0_TX_FLOW_CTRL_TFE; + WR4(sc, GMAC_MAC_Q0_TX_FLOW_CTRL, reg); + if (bootverbose) + device_printf(dev, "GMAC_TX_FLOW %x\n", reg); + + reg = RD4(sc, GMAC_MAC_RX_FLOW_CTRL); + reg |= GMAC_MAC_RX_FLOW_CTRL_RFE; + WR4(sc, GMAC_MAC_RX_FLOW_CTRL, reg); + if (bootverbose) + device_printf(dev, "GMAC_RX_FLOW %x\n", reg); + WR4(sc, GMAC_MAC_1US_TIC_COUNTER, (sc->csr_clock / 1000000) - 1); } @@ -241,8 +294,9 @@ eqos_media_change(if_t ifp) int error; EQOS_LOCK(sc); - error = mii_mediachg(device_get_softc(sc->miibus)); + error = mii_mediachg(device_get_softc(sc->miibus)); EQOS_UNLOCK(sc); + return (error); } @@ -259,7 +313,8 @@ eqos_setup_txdesc(struct eqos_softc *sc, int index, int flags, tdes2 = (flags & EQOS_TDES3_LD) ? EQOS_TDES2_IOC : 0; tdes3 = flags; } - bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, BUS_DMASYNC_PREWRITE); + + //bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, BUS_DMASYNC_PREWRITE); sc->tx.desc_ring[index].des0 = htole32((uint32_t)paddr); sc->tx.desc_ring[index].des1 = htole32((uint32_t)(paddr >> 32)); sc->tx.desc_ring[index].des2 = htole32(tdes2 | len); @@ -276,6 +331,7 @@ eqos_setup_txbuf(struct eqos_softc *sc, struct mbuf *m) error = bus_dmamap_load_mbuf_sg(sc->tx.buf_tag, sc->tx.buf_map[first].map, m, segs, &nsegs, 0); + if (error == EFBIG) { struct mbuf *mb; @@ -300,8 +356,11 @@ eqos_setup_txbuf(struct eqos_softc *sc, struct mbuf *m) BUS_DMASYNC_PREWRITE); sc->tx.buf_map[first].mbuf = m; + flags = EQOS_TDES3_FD; + if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) + flags |= EQOS_TDES3_CIC_FULL; - for (flags = EQOS_TDES3_FD, idx = 0; idx < nsegs; idx++) { + for (idx = 0; idx < nsegs; idx++) { if (idx == (nsegs - 1)) flags |= EQOS_TDES3_LD; eqos_setup_txdesc(sc, sc->tx.head, flags, segs[idx].ds_addr, @@ -315,7 +374,7 @@ eqos_setup_txbuf(struct eqos_softc *sc, struct mbuf *m) * Defer setting OWN bit on the first descriptor * until all descriptors have been updated */ - bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, BUS_DMASYNC_PREWRITE); + //bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, BUS_DMASYNC_PREWRITE); sc->tx.desc_ring[first].des3 |= htole32(EQOS_TDES3_OWN); return (0); @@ -324,11 +383,17 @@ eqos_setup_txbuf(struct eqos_softc *sc, struct mbuf *m) static void eqos_setup_rxdesc(struct eqos_softc *sc, int index, bus_addr_t paddr) { - sc->rx.desc_ring[index].des0 = htole32((uint32_t)paddr); sc->rx.desc_ring[index].des1 = htole32((uint32_t)(paddr >> 32)); sc->rx.desc_ring[index].des2 = htole32(0); - bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, BUS_DMASYNC_PREWRITE); + + sc->rx.desc_ring[index].des3 = htole32(EQOS_RDES3_OWN | EQOS_RDES3_IOC | + EQOS_RDES3_BUF1V); +} + +static void +eqos_reuse_rxdesc(struct eqos_softc *sc, int index) +{ sc->rx.desc_ring[index].des3 = htole32(EQOS_RDES3_OWN | EQOS_RDES3_IOC | EQOS_RDES3_BUF1V); } @@ -362,13 +427,13 @@ eqos_alloc_mbufcl(struct eqos_softc *sc) if ((m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR))) m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; + return (m); } static void eqos_enable_intr(struct eqos_softc *sc) { - WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, GMAC_DMA_CHAN0_INTR_ENABLE_NIE | GMAC_DMA_CHAN0_INTR_ENABLE_AIE | GMAC_DMA_CHAN0_INTR_ENABLE_FBE | GMAC_DMA_CHAN0_INTR_ENABLE_RIE | @@ -378,14 +443,12 @@ eqos_enable_intr(struct eqos_softc *sc) static void eqos_disable_intr(struct eqos_softc *sc) { - WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, 0); } static uint32_t eqos_bitrev32(uint32_t x) { - x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1)); x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2)); x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4)); @@ -402,6 +465,7 @@ eqos_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) crc &= 0x7f; crc = eqos_bitrev32(~crc) >> 26; hash[crc >> 5] |= 1 << (crc & 0x1f); + return (1); } @@ -420,6 +484,7 @@ eqos_setup_rxfilter(struct eqos_softc *sc) GMAC_MAC_PACKET_FILTER_PM | GMAC_MAC_PACKET_FILTER_HMC | GMAC_MAC_PACKET_FILTER_PCF_MASK); + hash[0] = hash[1] = 0xffffffff; if ((if_getflags(ifp) & IFF_PROMISC)) { @@ -485,6 +550,57 @@ eqos_init_rings(struct eqos_softc *sc) (uint32_t)sc->rx.desc_ring_paddr + DESC_OFFSET(RX_DESC_COUNT)); } +#define UBOOT_LEACH +#ifdef UBOOT_LEACH +#define GMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 0x6 +#define GMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0x0 +#define GMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f +#define GMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f +#define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 0x2 + +#define GMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16 +#define GMAC_DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f +#define GMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16 +#define GMAC_DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f + +static inline void +clrsetbits_le32(struct eqos_softc *sc, uint32_t addr, uint32_t clear, uint32_t set) +{ + WR4(sc, addr, (RD4(sc, addr) & (~clear)) | set); +} + +static inline void +setbits_le32(struct eqos_softc *sc, uint32_t addr, uint32_t set) +{ + clrsetbits_le32(sc, addr, set, set); +} +#endif + +static void +eqos_clean_dma_descs(struct eqos_softc *sc) +{ + int i; + + sc->tx.head = 0; + sc->tx.tail = 0; + for (i = 0; i < TX_DESC_COUNT; i++) { + eqos_setup_txdesc(sc, i, 0, 0, 0, 0); + } + bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, BUS_DMASYNC_PREWRITE); + + bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + sc->rx.head = 0; + sc->rx.tail = 0; + for (i = 0; i < TX_DESC_COUNT; i++) { + if(le32toh(sc->rx.desc_ring[i].des3) & EQOS_RDES3_OWN) + continue; + eqos_setup_rxbuf(sc, i, sc->rx.buf_map[i].mbuf); + } + + bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, BUS_DMASYNC_PREWRITE); +} + static void eqos_init(void *if_softc) { @@ -492,6 +608,9 @@ eqos_init(void *if_softc) if_t ifp = sc->ifp; struct mii_data *mii = device_get_softc(sc->miibus); uint32_t val; +#ifdef UBOOT_LEACH + uint32_t rx_fifo_sz, tx_fifo_sz, rqs, tqs, pbl; +#endif if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) return; @@ -504,6 +623,121 @@ eqos_init(void *if_softc) WR4(sc, GMAC_MAC_1US_TIC_COUNTER, (sc->csr_clock / 1000000) - 1); + /* Disable counters */ + WR4(sc, GMAC_MMC_CONTROL, + GMAC_MMC_CONTROL_CNTFREEZ | + GMAC_MMC_CONTROL_CNTPRST | + GMAC_MMC_CONTROL_CNTPRSTLVL); + +#ifndef UBOOT_LEACH + /* Configure operation modes */ + WR4(sc, GMAC_MTL_TXQ0_OPERATION_MODE, + GMAC_MTL_TXQ0_OPERATION_MODE_TSF | + GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_EN); + WR4(sc, GMAC_MTL_RXQ0_OPERATION_MODE, + GMAC_MTL_RXQ0_OPERATION_MODE_RSF | + GMAC_MTL_RXQ0_OPERATION_MODE_FEP | + GMAC_MTL_RXQ0_OPERATION_MODE_FUP); +#else + /* Configure MTL */ + + /* Enable Store and Forward mode for TX */ + /* Program Tx operating mode */ + setbits_le32(sc, GMAC_MTL_TXQ0_OPERATION_MODE, + GMAC_MTL_TXQ0_OPERATION_MODE_TSF | + (GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED << + GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT)); + + /* Transmit Queue weight */ + WR4(sc, GMAC_MTL_TXQ0_QUANTUM_WEIGHT, 0x10); + + /* Enable Store and Forward mode for RX, since no jumbo frame */ + setbits_le32(sc, GMAC_MTL_RXQ0_OPERATION_MODE, + GMAC_MTL_RXQ0_OPERATION_MODE_RSF); + + /* Transmit/Receive queue fifo size; use all RAM for 1 queue */ + val = sc->hw_feature[1]; + tx_fifo_sz = (val >> GMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) & + GMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK; + rx_fifo_sz = (val >> GMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) & + GMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK; + + /* r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting */ + tx_fifo_sz = 128 << tx_fifo_sz; + rx_fifo_sz = 128 << rx_fifo_sz; + + /* Allow platform to override TX/RX fifo size */ + + /* r/tqs is encoded as (n / 256) - 1 */ + tqs = tx_fifo_sz / 256 - 1; + rqs = rx_fifo_sz / 256 - 1; + + clrsetbits_le32(sc, GMAC_MTL_TXQ0_OPERATION_MODE, + GMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK << + GMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT, + tqs << GMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT); + clrsetbits_le32(sc, GMAC_MTL_RXQ0_OPERATION_MODE, + GMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK << + GMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT, + rqs << GMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT); + + if (rqs >= ((4096 / 256) - 1)) { + uint32_t rfd, rfa; + + setbits_le32(sc, GMAC_MTL_RXQ0_OPERATION_MODE, + GMAC_MTL_RXQ0_OPERATION_MODE_EHFC); + + /* + * Set Threshold for Activating Flow Contol space for min 2 + * frames ie, (1500 * 1) = 1500 bytes. + * + * Set Threshold for Deactivating Flow Contol for space of + * min 1 frame (frame size 1500bytes) in receive fifo + */ + if (rqs == ((4096 / 256) - 1)) { + /* + * This violates the above formula because of FIFO size + * limit therefore overflow may occur inspite of this. + */ + rfd = 0x3; /* Full-3K */ + rfa = 0x1; /* Full-1.5K */ + } else if (rqs == ((8192 / 256) - 1)) { + rfd = 0x6; /* Full-4K */ + rfa = 0xa; /* Full-6K */ + } else if (rqs == ((16384 / 256) - 1)) { + rfd = 0x6; /* Full-4K */ + rfa = 0x12; /* Full-10K */ + } else { + rfd = 0x6; /* Full-4K */ + rfa = 0x1E; /* Full-16K */ + } + + clrsetbits_le32(sc, GMAC_MTL_RXQ0_OPERATION_MODE, + (GMAC_MTL_RXQ0_OPERATION_MODE_RFD_MASK << + GMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) | + (GMAC_MTL_RXQ0_OPERATION_MODE_RFA_MASK << + GMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT), + (rfd << + GMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) | + (rfa << + GMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT)); + } + + if (bootverbose) + device_printf(sc->dev,"tx_fifo_sz=%u rx_fifo_sz=%u tqs=%u rqs=%u\n", + tx_fifo_sz, rx_fifo_sz, tqs, rqs); + + pbl = tqs + 1; + clrsetbits_le32(sc, GMAC_DMA_CHAN0_TX_CONTROL, + GMAC_DMA_CH0_TX_CONTROL_TXPBL_MASK << + GMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT, + pbl << GMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT); + + clrsetbits_le32(sc, GMAC_DMA_CHAN0_RX_CONTROL, + GMAC_DMA_CH0_RX_CONTROL_RXPBL_MASK << + GMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT, + 8 << GMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT); +#endif /* Enable transmit and receive DMA */ val = RD4(sc, GMAC_DMA_CHAN0_CONTROL); val &= ~GMAC_DMA_CHAN0_CONTROL_DSL_MASK; @@ -520,26 +754,12 @@ eqos_init(void *if_softc) val |= GMAC_DMA_CHAN0_RX_CONTROL_START; WR4(sc, GMAC_DMA_CHAN0_RX_CONTROL, val); - /* Disable counters */ - WR4(sc, GMAC_MMC_CONTROL, - GMAC_MMC_CONTROL_CNTFREEZ | - GMAC_MMC_CONTROL_CNTPRST | - GMAC_MMC_CONTROL_CNTPRSTLVL); - - /* Configure operation modes */ - WR4(sc, GMAC_MTL_TXQ0_OPERATION_MODE, - GMAC_MTL_TXQ0_OPERATION_MODE_TSF | - GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_EN); - WR4(sc, GMAC_MTL_RXQ0_OPERATION_MODE, - GMAC_MTL_RXQ0_OPERATION_MODE_RSF | - GMAC_MTL_RXQ0_OPERATION_MODE_FEP | - GMAC_MTL_RXQ0_OPERATION_MODE_FUP); - /* Enable flow control */ val = RD4(sc, GMAC_MAC_Q0_TX_FLOW_CTRL); val |= 0xFFFFU << GMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT; val |= GMAC_MAC_Q0_TX_FLOW_CTRL_TFE; WR4(sc, GMAC_MAC_Q0_TX_FLOW_CTRL, val); + val = RD4(sc, GMAC_MAC_RX_FLOW_CTRL); val |= GMAC_MAC_RX_FLOW_CTRL_RFE; WR4(sc, GMAC_MAC_RX_FLOW_CTRL, val); @@ -604,7 +824,6 @@ eqos_start_locked(if_t ifp) if (pending) { bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); - /* Start and run TX DMA */ WR4(sc, GMAC_DMA_CHAN0_TX_END_ADDR, (uint32_t)sc->tx.desc_ring_paddr + DESC_OFFSET(sc->tx.head)); @@ -634,7 +853,7 @@ eqos_stop(struct eqos_softc *sc) if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING | IFF_DRV_OACTIVE); callout_stop(&sc->callout); - + callout_stop(&sc->calltxi); /* Disable receiver */ val = RD4(sc, GMAC_MAC_CONFIGURATION); val &= ~GMAC_MAC_CONFIGURATION_RE; @@ -654,12 +873,14 @@ eqos_stop(struct eqos_softc *sc) val = RD4(sc, GMAC_MTL_TXQ0_OPERATION_MODE); val |= GMAC_MTL_TXQ0_OPERATION_MODE_FTQ; WR4(sc, GMAC_MTL_TXQ0_OPERATION_MODE, val); + for (retry = 10000; retry > 0; retry--) { val = RD4(sc, GMAC_MTL_TXQ0_OPERATION_MODE); if (!(val & GMAC_MTL_TXQ0_OPERATION_MODE_FTQ)) break; DELAY(10); } + if (!retry) device_printf(sc->dev, "timeout flushing TX queue\n"); @@ -668,6 +889,7 @@ eqos_stop(struct eqos_softc *sc) val &= ~GMAC_MAC_CONFIGURATION_TE; WR4(sc, GMAC_MAC_CONFIGURATION, val); + eqos_clean_dma_descs(sc); eqos_disable_intr(sc); EQOS_UNLOCK(sc); @@ -677,39 +899,78 @@ static void eqos_rxintr(struct eqos_softc *sc) { if_t ifp = sc->ifp; - struct mbuf *m; - uint32_t rdes3; - int error, length; + struct mbuf *m, *mh, *mt; + uint32_t rdes3, rdes1; + int error, length, one = 0, cnt; + + cnt = 0; + mh = NULL; + mt = NULL; + + bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); while (true) { rdes3 = le32toh(sc->rx.desc_ring[sc->rx.head].des3); if ((rdes3 & EQOS_RDES3_OWN)) break; - if (rdes3 & (EQOS_RDES3_OE | EQOS_RDES3_RE)) + one = 1; + + error = rdes3 & (EQOS_RDES3_OE | EQOS_RDES3_RE); + if(error) printf("Receive errer rdes3=%08x\n", rdes3); + length = rdes3 & EQOS_RDES3_LENGTH_MASK; + if(!length) { + printf("E0\n"); + eqos_reuse_rxdesc(sc, sc->rx.head); + if(error) + if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); + continue; + } + bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[sc->rx.head].map, BUS_DMASYNC_POSTREAD); bus_dmamap_unload(sc->rx.buf_tag, sc->rx.buf_map[sc->rx.head].map); - length = rdes3 & EQOS_RDES3_LENGTH_MASK; - if (length) { - m = sc->rx.buf_map[sc->rx.head].mbuf; - m->m_pkthdr.rcvif = ifp; - m->m_pkthdr.len = length; - m->m_len = length; - m->m_nextpkt = NULL; - - /* Remove trailing FCS */ - m_adj(m, -ETHER_CRC_LEN); - - EQOS_UNLOCK(sc); - if_input(ifp, m); - EQOS_LOCK(sc); + m = sc->rx.buf_map[sc->rx.head].mbuf; + m->m_pkthdr.rcvif = ifp; + m->m_pkthdr.len = length; + m->m_len = length; + m->m_nextpkt = NULL; + + rdes1 = le32toh(sc->rx.desc_ring[sc->rx.head].des1); + if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 && + (rdes1 & EQOS_RDES1_IPV4_HEADER) != 0) { + m->m_pkthdr.csum_flags = CSUM_IP_CHECKED; + if((rdes1 & EQOS_RDES1_IP_HDR_ERROR) == 0) + m->m_pkthdr.csum_flags |= CSUM_IP_VALID; + if((rdes1 & EQOS_RDES1_IP_CSUM_ERROR) == 0) { + m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR; + m->m_pkthdr.csum_data = 0xffff; + } } + /* Remove trailing FCS */ + m_adj(m, -ETHER_CRC_LEN); + m->m_nextpkt = NULL; + if (mh == NULL) + mh = m; + else + mt->m_nextpkt = m; + mt = m; + ++cnt; + + if (cnt == 64) { + EQOS_UNLOCK(sc); + if_input(ifp, mh); + EQOS_LOCK(sc); + mh = mt = NULL; + cnt = 0; + } + if ((m = eqos_alloc_mbufcl(sc))) { if ((error = eqos_setup_rxbuf(sc, sc->rx.head, m))) printf("ERROR: Hole in RX ring!!\n"); @@ -718,22 +979,33 @@ eqos_rxintr(struct eqos_softc *sc) if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); + sc->rx.head = RX_NEXT(sc->rx.head); + } + if(one) { WR4(sc, GMAC_DMA_CHAN0_RX_END_ADDR, (uint32_t)sc->rx.desc_ring_paddr + DESC_OFFSET(sc->rx.head)); - - sc->rx.head = RX_NEXT(sc->rx.head); + bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, + BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); + if (mh != NULL) { + EQOS_UNLOCK(sc); + if_input(ifp, mh); + EQOS_LOCK(sc); + } } } static void -eqos_txintr(struct eqos_softc *sc) +eqos_txintr(void *arg) { + struct eqos_softc *sc = (struct eqos_softc *)arg; if_t ifp = sc->ifp; struct eqos_bufmap *bmap; - uint32_t tdes3; + uint32_t tdes3, one = 0; EQOS_ASSERT_LOCKED(sc); + bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); while (sc->tx.tail != sc->tx.head) { tdes3 = le32toh(sc->tx.desc_ring[sc->tx.tail].des3); @@ -744,20 +1016,21 @@ eqos_txintr(struct eqos_softc *sc) if (bmap->mbuf) { bus_dmamap_sync(sc->tx.buf_tag, bmap->map, BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->tx.buf_tag, bmap->map); m_freem(bmap->mbuf); bmap->mbuf = NULL; } eqos_setup_txdesc(sc, sc->tx.tail, 0, 0, 0, 0); - - if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); + one = 1; /* Last descriptor in a packet contains DMA status */ if ((tdes3 & EQOS_TDES3_LD)) { if ((tdes3 & EQOS_TDES3_DE)) { if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); } else if ((tdes3 & EQOS_TDES3_ES)) { + device_printf(sc->dev, "dma tx err: %08x\n", tdes3); if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); } else { if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); @@ -765,8 +1038,17 @@ eqos_txintr(struct eqos_softc *sc) } sc->tx.tail = TX_NEXT(sc->tx.tail); } + + if(one) + if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); + if (sc->tx.tail == sc->tx.head) sc->tx_watchdog = 0; + else + if (TX_QUEUED(sc->tx.head, sc->tx.tail)) { + callout_reset_sbt(&sc->calltxi, SBT_1US * 300, 0, eqos_txintr, sc, 0); + } + eqos_start_locked(sc->ifp); } @@ -848,8 +1130,8 @@ eqos_intr(void *arg) if (dma_status & GMAC_DMA_CHAN0_STATUS_RI) eqos_rxintr(sc); - if (dma_status & GMAC_DMA_CHAN0_STATUS_TI) - eqos_txintr(sc); + if (dma_status & GMAC_DMA_CHAN0_STATUS_TI) + eqos_txintr(sc); EQOS_UNLOCK(sc); @@ -860,6 +1142,7 @@ eqos_intr(void *arg) RD4(sc, GMAC_MTL_INTERRUPT_STATUS), RD4(sc, GMAC_DMA_CHAN0_STATUS)); } + if ((rx_tx_status = RD4(sc, GMAC_MAC_RX_TX_STATUS))) device_printf(sc->dev, "RX/TX status interrupt\n"); } @@ -946,6 +1229,7 @@ eqos_get_eaddr(struct eqos_softc *sc, uint8_t *eaddr) maclo = 0xf2 | (arc4random() & 0xffff0000); machi = arc4random() & 0x0000ffff; } + eaddr[0] = maclo & 0xff; eaddr[1] = (maclo >> 8) & 0xff; eaddr[2] = (maclo >> 16) & 0xff; @@ -958,32 +1242,59 @@ static void eqos_axi_configure(struct eqos_softc *sc) { uint32_t val; + uint8_t wr8 = 0x4, rd8 = 0x8; + uint16_t blen[AXI_BLEN] = { 0, 0, 0, 0, 16, 8, 4}; + int i; +#ifdef FDT + wr8 = sc->axi_wr_osr_lmt; + rd8 = sc->axi_rd_osr_lmt; + memcpy(blen, sc->axi_blen, sizeof(blen)); +#endif val = RD4(sc, GMAC_DMA_SYSBUS_MODE); /* Max Write Outstanding Req Limit */ val &= ~GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK; - val |= 0x03 << GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT; + val |= wr8 << GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT; /* Max Read Outstanding Req Limit */ val &= ~GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK; - val |= 0x07 << GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT; + val |= rd8 << GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT; /* Allowed Burst Length's */ - val |= GMAC_DMA_SYSBUS_MODE_BLEN16; - val |= GMAC_DMA_SYSBUS_MODE_BLEN8; - val |= GMAC_DMA_SYSBUS_MODE_BLEN4; - + for (i = 0; i < AXI_BLEN; i++) { + switch (blen[i]) { + case 256: + val |= GMAC_DMA_SYSBUS_MODE_BLEN256; + break; + case 128: + val |= GMAC_DMA_SYSBUS_MODE_BLEN128; + break; + case 64: + val |= GMAC_DMA_SYSBUS_MODE_BLEN64; + break; + case 32: + val |= GMAC_DMA_SYSBUS_MODE_BLEN32; + break; + case 16: + val |= GMAC_DMA_SYSBUS_MODE_BLEN16; + break; + case 8: + val |= GMAC_DMA_SYSBUS_MODE_BLEN8; + break; + case 4: + val |= GMAC_DMA_SYSBUS_MODE_BLEN4; + break; + } + } /* Fixed Burst Length */ val |= GMAC_DMA_SYSBUS_MODE_MB; - WR4(sc, GMAC_DMA_SYSBUS_MODE, val); } static void eqos_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) { - if (!error) *(bus_addr_t *)arg = segs[0].ds_addr; } @@ -1025,7 +1336,7 @@ eqos_setup_dma(struct eqos_softc *sc) if ((error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, - MCLBYTES*TX_MAX_SEGS, TX_MAX_SEGS, + MCLBYTES * TX_MAX_SEGS, TX_MAX_SEGS, MCLBYTES, 0, NULL, NULL, &sc->tx.buf_tag))) { device_printf(sc->dev, "could not create TX buffer DMA tag.\n"); @@ -1095,6 +1406,7 @@ eqos_setup_dma(struct eqos_softc *sc) } } + bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, BUS_DMASYNC_PREWRITE); if (bootverbose) device_printf(sc->dev, "TX ring @ 0x%lx, RX ring @ 0x%lx\n", sc->tx.desc_ring_paddr, sc->rx.desc_ring_paddr); @@ -1106,7 +1418,7 @@ eqos_attach(device_t dev) { struct eqos_softc *sc = device_get_softc(dev); if_t ifp; - uint32_t ver; + uint32_t ver, val; uint8_t eaddr[ETHER_ADDR_LEN]; u_int userver, snpsver; int error; @@ -1119,12 +1431,15 @@ eqos_attach(device_t dev) return (ENXIO); } + if ((error = IF_EQOS_INIT(dev))) + return (error); + sc->dev = dev; ver = RD4(sc, GMAC_MAC_VERSION); userver = (ver & GMAC_MAC_VERSION_USERVER_MASK) >> GMAC_MAC_VERSION_USERVER_SHIFT; - snpsver = ver & GMAC_MAC_VERSION_SNPSVER_MASK; + snpsver = ver & GMAC_MAC_VERSION_SNPSVER_MASK; if (snpsver != 0x51) { device_printf(dev, "EQOS version 0x%02xx not supported\n", snpsver); @@ -1142,12 +1457,9 @@ eqos_attach(device_t dev) sc->hw_feature[2], sc->hw_feature[3]); } - - if ((error = IF_EQOS_INIT(dev))) - return (error); - mtx_init(&sc->lock, "eqos lock", MTX_NETWORK_LOCK, MTX_DEF); callout_init_mtx(&sc->callout, &sc->lock, 0); + callout_init_mtx(&sc->calltxi, &sc->lock, 0); eqos_get_eaddr(sc, eaddr); if (bootverbose) @@ -1186,13 +1498,25 @@ eqos_attach(device_t dev) if_setinitfn(ifp, eqos_init); if_setsendqlen(ifp, TX_DESC_COUNT - 1); if_setsendqready(ifp); - if_setcapabilities(ifp, IFCAP_VLAN_MTU /*| IFCAP_HWCSUM*/); + + val = IFCAP_VLAN_MTU; + if(sc->hw_feature[0] & GMAC_HW_FEAT_TXCOSEL) { + val |= IFCAP_TXCSUM; + if_sethwassist(sc->ifp, CSUM_IP | CSUM_UDP | CSUM_TCP); + } + + if(sc->hw_feature[0] & GMAC_HW_FEAT_RXCOESEL) + val |= IFCAP_RXCSUM; + + if_setcapabilities(sc->ifp, val); if_setcapenable(ifp, if_getcapabilities(ifp)); + eqos_enable_csum_offload(sc); + /* Attach MII driver */ if ((error = mii_attach(sc->dev, &sc->miibus, ifp, eqos_media_change, eqos_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, - MII_OFFSET_ANY, 0))) { + MII_OFFSET_ANY, MIIF_NOISOLATE * 0))) { device_printf(sc->dev, "PHY attach failed\n"); return (ENXIO); } @@ -1219,6 +1543,7 @@ eqos_detach(device_t dev) if (sc->miibus) device_delete_child(dev, sc->miibus); + bus_generic_detach(dev); if (sc->irq_handle) @@ -1246,7 +1571,6 @@ eqos_detach(device_t dev) } bus_dma_tag_destroy(sc->tx.buf_tag); } - if (sc->rx.desc_tag) { if (sc->rx.desc_map) { bus_dmamap_unload(sc->rx.desc_tag, sc->rx.desc_map); @@ -1263,13 +1587,15 @@ eqos_detach(device_t dev) } bus_dma_tag_destroy(sc->rx.buf_tag); } - +#ifdef FDT + if(sc->clks) + free(sc->clks, M_DEVBUF); +#endif mtx_destroy(&sc->lock); return (0); } - static device_method_t eqos_methods[] = { /* Device Interface */ DEVMETHOD(device_attach, eqos_attach), diff --git a/sys/dev/eqos/if_eqos_fdt.c b/sys/dev/eqos/if_eqos_fdt.c index 6d6c80bd2e92..0b7deb0a0f11 100644 --- a/sys/dev/eqos/if_eqos_fdt.c +++ b/sys/dev/eqos/if_eqos_fdt.c @@ -46,10 +46,12 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -61,15 +63,12 @@ #include "gpio_if.h" #include "rk_otp_if.h" -#define RK356XGMAC0 0xfe2a0000 -#define RK356XGMAC1 0xfe010000 -#define RK3588GMAC0 0xfe1b0000 -#define RK3588GMAC1 0xfe1c0000 +#define RK_MASK_HIGH(val, mask, shift) \ + (((val) << (shift)) | (mask) << ((shift) + 16)) + +#define RK_BITS(n) ((1 << (n)) | (1 << ((n) + 16))) +#define RK_HI_BITS(n) ((1 << ((n) + 16))) -#define EQOS_GRF_GMAC0 0x0380 -#define EQOS_GRF_GMAC1 0x0388 -#define EQOS_CON0_OFFSET 0 -#define EQOS_CON1_OFFSET 4 #define EQOS_GMAC_PHY_INTF_SEL_RGMII 0x00fc0010 #define EQOS_GMAC_PHY_INTF_SEL_RMII 0x00fc0040 @@ -82,11 +81,318 @@ #define WR4(sc, o, v) bus_write_4(sc->res[EQOS_RES_MEM], (o), (v)) +struct eqos_ops { + int (*set_to_rgmii)(device_t dev,int tx_delay, int rx_delay); + int (*set_to_rmii)(device_t dev); + int (*set_rgmii_speed)(device_t dev, int speed); + int (*set_rmii_speed)(device_t dev, int speed); + int (*set_clock_selection)(device_t dev, bool input); + bool regs_valid; + uint32_t regs[]; +}; + +static const char * eqos_clocks[] = { + "aclk_mac", "pclk_mac", /*"mac_clk_tx",*/ "clk_mac_speed", +}; + +static const char * eqos_rmii_clocks[] = { + "mac_clk_rx", "clk_mac_ref", "clk_mac_refout", +}; + +enum eqos_clk_index { + EQOS_ACLK_MAC = 0, + EQOS_PCLK_MAC, +/* EQOS_MAC_CLK_TX,*/ + EQOS_CLK_MAC_SPEED, + EQOS_MAC_CLK_RX, + EQOS_CLK_MAC_REF, + EQOS_CLK_MAC_REFOUT, +}; + +#define RK3568_GRF_GMAC0_CON0 0x0380 +#define RK3568_GRF_GMAC0_CON1 0x0384 +#define RK3568_GRF_GMAC1_CON0 0x0388 +#define RK3568_GRF_GMAC1_CON1 0x038c + +/* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */ +#define RK3568_GMAC_PHY_INTF_SEL_RGMII \ + (RK_BITS(4) | RK_HI_BITS(5) | RK_HI_BITS(6)) +#define RK3568_GMAC_PHY_INTF_SEL_RMII \ + (RK_HI_BITS(4) | RK_HI_BITS(5) | RK_BITS(6)) +#define RK3568_GMAC_FLOW_CTRL RK_BITS(3) +#define RK3568_GMAC_FLOW_CTRL_CLR RK_HI_BITS(3) +#define RK3568_GMAC_RXCLK_DLY_ENABLE RK_BITS(1) +#define RK3568_GMAC_RXCLK_DLY_DISABLE RK_HI_BITS(1) +#define RK3568_GMAC_TXCLK_DLY_ENABLE RK_BITS(0) +#define RK3568_GMAC_TXCLK_DLY_DISABLE RK_HI_BITS(0) + +/* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */ +#define RK3568_GMAC_CLK_RX_DL_CFG(val) RK_MASK_HIGH(val, 0x7F, 8) +#define RK3568_GMAC_CLK_TX_DL_CFG(val) RK_MASK_HIGH(val, 0x7F, 0) + +static int +rk3568_set_rgmii(device_t dev, int tx_delay, int rx_delay) +{ + struct eqos_softc *sc = device_get_softc(dev); + uint32_t reg0, reg1; + + reg0 = (sc->idx == 1) ? RK3568_GRF_GMAC1_CON0 : + RK3568_GRF_GMAC0_CON0; + reg1 = (sc->idx == 1) ? RK3568_GRF_GMAC1_CON1 : + RK3568_GRF_GMAC0_CON1; + + SYSCON_WRITE_4(sc->grf, reg0, + RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) | + RK3568_GMAC_CLK_TX_DL_CFG(tx_delay)); + + SYSCON_WRITE_4(sc->grf, reg1, + RK3568_GMAC_PHY_INTF_SEL_RGMII | + RK3568_GMAC_RXCLK_DLY_ENABLE | + RK3568_GMAC_TXCLK_DLY_ENABLE); + return (0); +} + +static int +rk3568_set_rmii(device_t dev) +{ + struct eqos_softc *sc = device_get_softc(dev); + uint32_t reg1; + + reg1 = (sc->idx == 1) ? RK3568_GRF_GMAC1_CON1 : + RK3568_GRF_GMAC0_CON1; + + SYSCON_WRITE_4(sc->grf, reg1, RK3568_GMAC_PHY_INTF_SEL_RMII); + + return (0); +} + +static int +rk3568_set_speed(device_t dev, int speed) +{ + struct eqos_softc *sc = device_get_softc(dev); + clk_t clk_mac_speed = sc->clks[EQOS_CLK_MAC_SPEED]; + unsigned long rate; + int error; + + switch (speed) { + case IFM_10_T: + rate = 2500000; + break; + case IFM_100_TX: + rate = 25000000; + break; + case IFM_1000_T: + case IFM_1000_SX: + rate = 125000000; + break; + default: + device_printf(dev, "unknown speed value for GMAC speed=%d", speed); + return (EINVAL); + } + + error = clk_set_freq(clk_mac_speed, rate, 0); + if(error) { + device_printf(dev, "can't set %s to %lu, return=%d\n", + clk_get_name(clk_mac_speed), rate, error); + } + + return (error); +} + +static const struct eqos_ops rk3568_ops = { + .set_to_rgmii = rk3568_set_rgmii, + .set_to_rmii = rk3568_set_rmii, + .set_rgmii_speed = rk3568_set_speed, + .set_rmii_speed = rk3568_set_speed, + .regs_valid = true, + .regs = { + 0xfe2a0000, /* gmac0 */ + 0xfe010000, /* gmac1 */ + 0x0, /* sentinel */ + }, +}; + +#define RK3588_GRF_GMAC_CON7 0x031c +#define RK3588_GRF_GMAC_CON8 0x0320 +#define RK3588_GRF_GMAC_CON9 0x0324 + +#define RK3588_GMAC_RXCLK_DLY_ENABLE(id) RK_BITS(2 * (id) + 3) +#define RK3588_GMAC_RXCLK_DLY_DISABLE(id) RK_HI_BITS(2 * (id) + 3) +#define RK3588_GMAC_TXCLK_DLY_ENABLE(id) RK_BITS(2 * (id) + 2) +#define RK3588_GMAC_TXCLK_DLY_DISABLE(id) RK_HI_BITS(2 * (id) + 2) + +#define RK3588_GMAC_CLK_RX_DL_CFG(val) RK_MASK_HIGH(val, 0xFF, 8) +#define RK3588_GMAC_CLK_TX_DL_CFG(val) RK_MASK_HIGH(val, 0xFF, 0) + +/* php_grf */ +#define RK3588_GRF_GMAC_CON0 0x0008 +#define RK3588_GRF_CLK_CON1 0x0070 + +#define RK3588_GMAC_PHY_INTF_SEL_RGMII(id) \ + (RK_BITS(3 + (id) * 6) | RK_HI_BITS(4 + (id) * 6) | RK_HI_BITS(5 + (id) * 6)) +#define RK3588_GMAC_PHY_INTF_SEL_RMII(id) \ + (RK_HI_BITS(3 + (id) * 6) | RK_HI_BITS(4 + (id) * 6) | RK_BITS(5 + (id) * 6)) + +#define RK3588_GMAC_CLK_RMII_MODE(id) RK_BITS(5 * (id)) +#define RK3588_GMAC_CLK_RGMII_MODE(id) RK_HI_BITS(5 * (id)) + +#define RK3588_GMAC_CLK_SELET_CRU(id) RK_BITS(5 * (id) + 4) +#define RK3588_GMAC_CLK_SELET_IO(id) RK_HI_BITS(5 * (id) + 4) + +#define RK3588_GMA_CLK_RMII_DIV2(id) RK_BITS(5 * (id) + 2) +#define RK3588_GMA_CLK_RMII_DIV20(id) RK_HI_BITS(5 * (id) + 2) + +#define RK3588_GMAC_CLK_RGMII_DIV1(id) \ + (RK_HI_BITS(5 * (id) + 2) | RK_HI_BITS(5 * (id) + 3)) +#define RK3588_GMAC_CLK_RGMII_DIV5(id) \ + (RK_BITS(5 * (id) + 2) | RK_BITS(5 * (id) + 3)) +#define RK3588_GMAC_CLK_RGMII_DIV50(id) \ + (RK_HI_BITS(5 * (id) + 2) | RK_BITS(5 * (id) + 3)) + +#define RK3588_GMAC_CLK_RMII_GATE(id) RK_BITS(5 * (id) + 1) +#define RK3588_GMAC_CLK_RMII_NOGATE(id) RK_HI_BITS(5 * (id) + 1) + +static int +rk3588_set_rgmii(device_t dev, int tx_delay, int rx_delay) +{ + struct eqos_softc *sc = device_get_softc(dev); + uint32_t offset_con, id = sc->idx; + + if (!(sc->php_grf)) { + device_printf(dev, "Missing rockchip,grf or rockchip,php_grf property\n"); + return (ENXIO); + } + + offset_con = id == 1 ? RK3588_GRF_GMAC_CON9 : + RK3588_GRF_GMAC_CON8; + + SYSCON_WRITE_4(sc->php_grf, RK3588_GRF_GMAC_CON0, + RK3588_GMAC_PHY_INTF_SEL_RGMII(id)); + + SYSCON_WRITE_4(sc->php_grf, RK3588_GRF_CLK_CON1, + RK3588_GMAC_CLK_RGMII_MODE(id)); + + SYSCON_WRITE_4(sc->grf, RK3588_GRF_GMAC_CON7, + RK3588_GMAC_RXCLK_DLY_ENABLE(id) | + RK3588_GMAC_TXCLK_DLY_ENABLE(id)); + + SYSCON_WRITE_4(sc->grf, offset_con, + RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) | + RK3588_GMAC_CLK_TX_DL_CFG(tx_delay)); + return (0); +} + +static int +rk3588_set_rmii(device_t dev) +{ + struct eqos_softc *sc = device_get_softc(dev); + + if (!sc->php_grf) { + device_printf(dev, "%s: Missing rockchip,php_grf property\n", __func__); + return ENXIO; + } + + SYSCON_WRITE_4(sc->php_grf, RK3588_GRF_GMAC_CON0, + RK3588_GMAC_PHY_INTF_SEL_RMII(sc->idx)); + + SYSCON_WRITE_4(sc->php_grf, RK3588_GRF_CLK_CON1, + RK3588_GMAC_CLK_RMII_MODE(sc->idx)); + + return (0); +} + +static int +rk3588_set_speed(device_t dev, int speed) +{ + struct eqos_softc *sc = device_get_softc(dev); + unsigned int val = 0, id = sc->idx; + + switch (speed) { + case IFM_10_T: + if (sc->phy_mode == MII_CONTYPE_RMII) + val = RK3588_GMA_CLK_RMII_DIV20(id); + else + val = RK3588_GMAC_CLK_RGMII_DIV50(id); + break; + case IFM_100_TX: + if (sc->phy_mode == MII_CONTYPE_RMII) + val = RK3588_GMA_CLK_RMII_DIV2(id); + else + val = RK3588_GMAC_CLK_RGMII_DIV5(id); + break; + case IFM_1000_T: + case IFM_1000_SX: + if (sc->phy_mode != MII_CONTYPE_RMII) + val = RK3588_GMAC_CLK_RGMII_DIV1(id); + else + goto err; + break; + default: + goto err; + } + + SYSCON_WRITE_4(sc->php_grf, RK3588_GRF_CLK_CON1, val); + + return (0); +err: + device_printf(dev, "unknown speed value for GMAC speed=%d", speed); + return (EINVAL); +} + +static int +rk3588_set_clock_selection(device_t dev, bool input) +{ + struct eqos_softc *sc = device_get_softc(dev); + unsigned int val = input ? RK3588_GMAC_CLK_SELET_IO(sc->idx) : + RK3588_GMAC_CLK_SELET_CRU(sc->idx); + + val |= RK3588_GMAC_CLK_RMII_NOGATE(sc->idx); + + SYSCON_WRITE_4(sc->php_grf, RK3588_GRF_CLK_CON1, val); + + return (0); +} + +static const struct eqos_ops rk3588_ops = { + .set_to_rgmii = rk3588_set_rgmii, + .set_to_rmii = rk3588_set_rmii, + .set_rgmii_speed = rk3588_set_speed, + .set_rmii_speed = rk3588_set_speed, + .set_clock_selection = rk3588_set_clock_selection, + .regs_valid = true, + .regs = { + 0xfe1b0000, /* gmac0 */ + 0xfe1c0000, /* gmac1 */ + 0x0, /* sentinel */ + }, +}; + static const struct ofw_compat_data compat_data[] = { - {"snps,dwmac-4.20a", 1}, + {"rockchip,rk3568-gmac", (uintptr_t) &rk3568_ops}, + {"rockchip,rk3588-gmac", (uintptr_t) &rk3588_ops}, { NULL, 0 } }; +static int +eqos_check_ops(device_t dev) +{ + struct eqos_softc *sc = device_get_softc(dev); + switch (sc->phy_mode) { + case MII_CONTYPE_RGMII: + case MII_CONTYPE_RGMII_ID: + case MII_CONTYPE_RGMII_RXID: + case MII_CONTYPE_RGMII_TXID: + if(!sc->ops->set_to_rgmii) + return (EINVAL); + break; + case MII_CONTYPE_RMII: + if(!sc->ops->set_to_rmii) + return (EINVAL); + break; + } + + return (0); +} static int eqos_phy_reset(device_t dev) @@ -119,7 +425,7 @@ eqos_phy_reset(device_t dev) if (GPIO_MAP_GPIOS(gpio, node, gpio_node, nitems(gpio_prop) - 1, - gpio_prop + 1, &pin, &flags) != 0) { + gpio_prop + 1, &pin, &flags) != 0) { device_printf(dev, "Can't map gpio for phy reset\n"); return (ENXIO); } @@ -139,6 +445,36 @@ eqos_phy_reset(device_t dev) return (0); } +static void +eqos_fdt_axi(device_t dev) +{ + phandle_t child, node = ofw_bus_get_node(dev); + struct eqos_softc *sc = device_get_softc(dev); + uint32_t blen[AXI_BLEN] = { 0, 0, 0, 0, 0x10, 0x8, 0x4}; + uint32_t temp; + int i; + + sc->axi_rd_osr_lmt = 8; + sc->axi_wr_osr_lmt = 16; + sc->axi_blen[6] = 0x4; + sc->axi_blen[5] = 0x8; + sc->axi_blen[4] = 0x16; + + child = ofw_bus_find_child(node, "stmmac-axi-config"); + if(child > 0) { + if (OF_getencprop(node, "snps,rd_osr_lmt", &temp, sizeof(temp)) == sizeof(temp)) + sc->axi_rd_osr_lmt = (uint8_t)temp; + + if (OF_getencprop(node, "snps,wr_osr_lmt", &temp, sizeof(temp)) == sizeof(temp)) + sc->axi_wr_osr_lmt = (uint8_t)temp; + + if (OF_getencprop(node, "snps,blen", blen, sizeof(blen)) == sizeof(blen)) { + for(i = 0; i < AXI_BLEN;i++) + sc->axi_blen[i] = blen[i]; + } + } +} + static int eqos_fdt_init(device_t dev) { @@ -147,27 +483,70 @@ eqos_fdt_init(device_t dev) hwreset_t eqos_reset; regulator_t eqos_supply; uint32_t rx_delay, tx_delay; + uint8_t buffer[16]; + const char *temp_name; + char *clock_in_out; + int i, error, n_clocks; + sc->ops = (struct eqos_ops *)ofw_bus_search_compatible(dev, compat_data)->ocd_data; if (OF_hasprop(node, "rockchip,grf") && syscon_get_by_ofw_property(dev, node, "rockchip,grf", &sc->grf)) { device_printf(dev, "cannot get grf driver handle\n"); return (ENXIO); } - /* figure out if gmac0 or gmac1 offset */ - switch (rman_get_start(sc->res[EQOS_RES_MEM])) { - case RK356XGMAC0: /* RK356X gmac0 */ - sc->grf_offset = EQOS_GRF_GMAC0; - break; - case RK356XGMAC1: /* RK356X gmac1 */ - sc->grf_offset = EQOS_GRF_GMAC1; - break; - case RK3588GMAC0: /* RK3588 gmac0 */ - case RK3588GMAC1: /* RK3588 gmac1 */ - default: - device_printf(dev, "Unknown eqos address\n"); - return (ENXIO); + if (OF_hasprop(node, "rockchip,php-grf")) + syscon_get_by_ofw_property(dev, node, "rockchip,php-grf", &sc->php_grf); + + /* detect gmac index */ + if(sc->ops->regs_valid) { + i = 0; + while(sc->ops->regs[i]) { + if(sc->ops->regs[i] == rman_get_start(sc->res[EQOS_RES_MEM])) { + sc->idx = i; + break; + } + i++; + } + } + + sc->phy_mode = mii_fdt_get_contype(node); + sc->clock_in = true; + + if (OF_getprop_alloc(node, "clock_in_out", (void **)&clock_in_out)) { + if (strcmp(clock_in_out, "input") == 0) + sc->clock_in = true; + else + sc->clock_in = false; + OF_prop_free(clock_in_out); + } + + /* Set the assigned clocks parent and freq + easier to control clock from cru / phy=external mess + */ + + if (clk_set_assigned(dev, node) != 0) { + device_printf(dev, "clk_set_assigned failed\n"); + goto fail; + } + + error = clk_get_by_ofw_name(dev, 0, "stmmaceth", &sc->clk_stmmaceth); + if (error != 0) { + device_printf(dev, "could not find clock stmmaceth\n"); + return (error); + } + + error = clk_enable(sc->clk_stmmaceth); + if(error) { + device_printf(dev, "could not enable clock stmmaceth\n"); + return (error); + } + + if(sc->clock_in) + device_printf(dev, "Clock input from the PHY\n"); + else if(sc->phy_mode == MII_CONTYPE_RMII) { + clk_set_freq(sc->clk_stmmaceth, 50000000, 0); } if (hwreset_get_by_ofw_idx(dev, node, 0, &eqos_reset)) { @@ -177,24 +556,19 @@ eqos_fdt_init(device_t dev) else hwreset_assert(eqos_reset); + if (OF_hasprop(node, "snps,force_thresh_dma_mode")) { + sc->force_thresh_dma_mode = 1; + } + sc->csr_clock = 125000000; - sc->csr_clock_range = GMAC_MAC_MDIO_ADDRESS_CR_100_150; + sc->csr_clock_range = GMAC_MAC_MDIO_ADDRESS_CR_100_150; //GMAC_MAC_MDIO_ADDRESS_CR_250_300; if (OF_getencprop(node, "tx_delay", &tx_delay, sizeof(tx_delay)) <= 0) tx_delay = 0x30; if (OF_getencprop(node, "rx_delay", &rx_delay, sizeof(rx_delay)) <= 0) rx_delay = 0x10; - SYSCON_WRITE_4(sc->grf, sc->grf_offset + EQOS_CON0_OFFSET, - EQOS_GMAC_CLK_RX_DL_CFG(rx_delay) | - EQOS_GMAC_CLK_TX_DL_CFG(tx_delay)); - SYSCON_WRITE_4(sc->grf, sc->grf_offset + EQOS_CON1_OFFSET, - EQOS_GMAC_PHY_INTF_SEL_RGMII | - EQOS_GMAC_RXCLK_DLY_ENABLE | - EQOS_GMAC_TXCLK_DLY_ENABLE); - - if (!regulator_get_by_ofw_property(dev, 0, "phy-supply", - &eqos_supply)) { + if (!regulator_get_by_ofw_property(dev, 0, "phy-supply", &eqos_supply)) { if (regulator_enable(eqos_supply)) device_printf(dev, "cannot enable 'phy' regulator\n"); } @@ -207,6 +581,64 @@ eqos_fdt_init(device_t dev) if (eqos_reset) hwreset_deassert(eqos_reset); + n_clocks = nitems(eqos_clocks); + if(sc->phy_mode == MII_CONTYPE_RMII) + n_clocks += nitems(eqos_rmii_clocks); + + sc->clks = (clk_t *)malloc(sizeof(clk_t) * n_clocks, M_DEVBUF, M_WAITOK | M_ZERO); + if(!sc->clks) { + device_printf(dev,"Failed clocks malloc\n"); + return (ENXIO); + } + + for(i = 0; i < n_clocks;i++) { + temp_name = (i < nitems(eqos_clocks)) ? eqos_clocks[i] : eqos_rmii_clocks[i - nitems(eqos_clocks)]; + if (clk_get_by_ofw_name(dev, 0, temp_name, &sc->clks[i]) != 0) { + device_printf(dev, "Can't get clock %s\n", temp_name); + goto fail; + } + } + + for(i = 0; i < n_clocks;i++) { + error = clk_enable(sc->clks[i]); + if(error) { + device_printf(dev, "Cannot enable clock %s\n",clk_get_name(sc->clks[i])); + goto fail; + } + } + + if(sc->ops->set_clock_selection) { + sc->ops->set_clock_selection(dev, sc->clock_in); + } + + error = eqos_check_ops(dev); + if(error) + goto fail; + + switch (sc->phy_mode) { + case MII_CONTYPE_RGMII: + error = sc->ops->set_to_rgmii(dev, tx_delay, rx_delay); + break; + case MII_CONTYPE_RGMII_ID: + error = sc->ops->set_to_rgmii(dev, 0, 0); + break; + case MII_CONTYPE_RGMII_RXID: + error = sc->ops->set_to_rgmii(dev, tx_delay, 0); + break; + case MII_CONTYPE_RGMII_TXID: + error = sc->ops->set_to_rgmii(dev, 0, rx_delay); + break; + case MII_CONTYPE_RMII: + error = sc->ops->set_to_rmii(dev); + break; + default: + device_printf(dev,"Unknown mii con type %d\n", sc->phy_mode); + error = ENXIO; + } + + if(error) + goto fail; + /* set the MAC address if we have OTP data handy */ if (!RK_OTP_READ(dev, buffer, 0, sizeof(buffer))) { uint32_t mac; @@ -220,13 +652,44 @@ eqos_fdt_init(device_t dev) htobe16((mac & 0x0000ffff) + (device_get_unit(dev) << 8))); } + eqos_fdt_axi(dev); return (0); +fail: + if(sc->clks) + free(sc->clks, M_DEVBUF); + + return (ENXIO); } static int -eqos_fdt_probe(device_t dev) +eqos_set_speed(device_t dev, int speed) { + struct eqos_softc *sc = device_get_softc(dev); + switch (sc->phy_mode) { + case MII_CONTYPE_RGMII: + case MII_CONTYPE_RGMII_ID: + case MII_CONTYPE_RGMII_RXID: + case MII_CONTYPE_RGMII_TXID: + if(sc->ops->set_rgmii_speed) + return sc->ops->set_rgmii_speed(dev, speed); + else + return (0); + break; + case MII_CONTYPE_RMII: + if(sc->ops->set_rmii_speed) + return sc->ops->set_rmii_speed(dev, speed); + else + return (0); + break; + default: + return (0); + } +} + +static int +eqos_fdt_probe(device_t dev) +{ if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) @@ -237,18 +700,18 @@ eqos_fdt_probe(device_t dev) return (BUS_PROBE_DEFAULT); } - static device_method_t eqos_fdt_methods[] = { /* Device interface */ DEVMETHOD(device_probe, eqos_fdt_probe), /* EQOS interface */ DEVMETHOD(if_eqos_init, eqos_fdt_init), + DEVMETHOD(if_eqos_set_speed, eqos_set_speed), DEVMETHOD_END }; -DEFINE_CLASS_1(eqos, eqos_fdt_driver, eqos_fdt_methods, +DEFINE_CLASS_1(eq, eqos_fdt_driver, eqos_fdt_methods, sizeof(struct eqos_softc), eqos_driver); DRIVER_MODULE(eqos, simplebus, eqos_fdt_driver, 0, 0); MODULE_DEPEND(eqos, ether, 1, 1, 1); diff --git a/sys/dev/eqos/if_eqos_reg.h b/sys/dev/eqos/if_eqos_reg.h index f9e7f9368cf2..53a3018a2ce1 100644 --- a/sys/dev/eqos/if_eqos_reg.h +++ b/sys/dev/eqos/if_eqos_reg.h @@ -36,6 +36,7 @@ #define _EQOS_REG_H #define GMAC_MAC_CONFIGURATION 0x0000 +#define GMAC_MAC_CONFIGURATION_IPC (1U << 27) #define GMAC_MAC_CONFIGURATION_CST (1U << 21) #define GMAC_MAC_CONFIGURATION_ACS (1U << 20) #define GMAC_MAC_CONFIGURATION_BE (1U << 18) @@ -96,6 +97,8 @@ #define GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT 14 #define GMAC_MAC_HW_FEATURE1_ADDR64_MASK (0x3U << GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT) #define GMAC_MAC_HW_FEATURE1_ADDR64_32BIT (0x0U << GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT) +#define GMAC_HW_FEAT_RXCOESEL (0x1U << 16) +#define GMAC_HW_FEAT_TXCOSEL (0x1U << 14) #define GMAC_MAC_MDIO_ADDRESS 0x0200 #define GMAC_MAC_MDIO_ADDRESS_PA_SHIFT 21 #define GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT 16 @@ -188,17 +191,47 @@ #define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_EN (2U << GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT) #define GMAC_MTL_TXQ0_OPERATION_MODE_TSF (1U << 1) #define GMAC_MTL_TXQ0_OPERATION_MODE_FTQ (1U << 0) +#define GMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ffU +#define GMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16 +#define GMAC_MTL_TXQ0_OPERATION_MODE_TTC_MASK (0x7 << 4) +#define GMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT 4 +#define GMAC_MTL_TXQ0_OPERATION_MODE_TTC_32 0 +#define GMAC_MTL_TXQ0_OPERATION_MODE_TTC_64 (1 << 4) +#define GMAC_MTL_TXQ0_OPERATION_MODE_TTC_96 (2 << 4) +#define GMAC_MTL_TXQ0_OPERATION_MODE_TTC_128 (3 << 4) +#define GMAC_MTL_TXQ0_OPERATION_MODE_TTC_192 (4 << 4) +#define GMAC_MTL_TXQ0_OPERATION_MODE_TTC_256 (5 << 4) +#define GMAC_MTL_TXQ0_OPERATION_MODE_TTC_384 (6 << 4) +#define GMAC_MTL_TXQ0_OPERATION_MODE_TTC_512 (7 << 4) +#define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_AV (1 << 2) #define GMAC_MTL_TXQ0_UNDERFLOW 0x0D04 #define GMAC_MTL_TXQ0_DEBUG 0x0D08 +#define GMAC_MTL_TXQ0_QUANTUM_WEIGHT 0x0D18 #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS 0x0D2C #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOIE (1U << 24) #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOVFIS (1U << 16) #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUIE (1U << 8) #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUNFIS (1U << 0) #define GMAC_MTL_RXQ0_OPERATION_MODE 0x0D30 + +#define GMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ffU +#define GMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20 +#define GMAC_MTL_RXQ0_OPERATION_MODE_RFD_MASK 0x3fU +#define GMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14 +#define GMAC_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3fU +#define GMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8 +#define GMAC_MTL_RXQ0_OPERATION_MODE_EHFC (1 << 7) + #define GMAC_MTL_RXQ0_OPERATION_MODE_RSF (1U << 5) #define GMAC_MTL_RXQ0_OPERATION_MODE_FEP (1U << 4) #define GMAC_MTL_RXQ0_OPERATION_MODE_FUP (1U << 3) +#define GMAC_MTL_RXQ0_OPERATION_MODE_RTC_MASK (0x3 << 3) +#define GMAC_MTL_RXQ0_OPERATION_MODE_RTC_SHIFT 3 +#define GMAC_MTL_RXQ0_OPERATION_MODE_RTC_32 (1 << 3) +#define GMAC_MTL_RXQ0_OPERATION_MODE_RTC_64 (0 << 3) +#define GMAC_MTL_RXQ0_OPERATION_MODE_RTC_96 (2 << 3) +#define GMAC_MTL_RXQ0_OPERATION_MODE_RTC_128 (3 << 3) + #define GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT 0x0D34 #define GMAC_MTL_RXQ0_DEBUG 0x0D38 #define GMAC_DMA_MODE 0x1000 @@ -210,6 +243,11 @@ #define GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK (0x7U << GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) #define GMAC_DMA_SYSBUS_MODE_MB (1U << 14) #define GMAC_DMA_SYSBUS_MODE_EAME (1U << 11) +#define AXI_BLEN 7 +#define GMAC_DMA_SYSBUS_MODE_BLEN256 (1U << 7) +#define GMAC_DMA_SYSBUS_MODE_BLEN128 (1U << 6) +#define GMAC_DMA_SYSBUS_MODE_BLEN64 (1U << 5) +#define GMAC_DMA_SYSBUS_MODE_BLEN32 (1U << 4) #define GMAC_DMA_SYSBUS_MODE_BLEN16 (1U << 3) #define GMAC_DMA_SYSBUS_MODE_BLEN8 (1U << 2) #define GMAC_DMA_SYSBUS_MODE_BLEN4 (1U << 1) @@ -283,6 +321,21 @@ #define EQOS_TDES3_DE (1U << 23) #define EQOS_TDES3_OE (1U << 21) #define EQOS_TDES3_ES (1U << 15) +#define EQOS_TDES3_CIC_FULL (3U << 16) + +#define EQOS_RDES1_IP_PAYLOAD_TYPE_MASK 0x7 +#define EQOS_RDES1_IP_HDR_ERROR (1U << 3) +#define EQOS_RDES1_IPV4_HEADER (1U << 4) +#define EQOS_RDES1_IPV6_HEADER (1U << 5) +#define EQOS_RDES1_IP_CSUM_BYPASSED (1U << 6) +#define EQOS_RDES1_IP_CSUM_ERROR (1U << 7) +#define EQOS_RDES1_PTP_MSG_TYPE_MASK (0xF << 8) +#define EQOS_RDES1_PTP_PACKET_TYPE (1U << 12) +#define EQOS_RDES1_PTP_VER (1U << 13) +#define EQOS_RDES1_TIMESTAMP_AVAILABLE (1U << 14) +#define EQOS_RDES1_TIMESTAMP_DROPPED (1U << 15) +#define EQOS_RDES1_IP_TYPE1_CSUM_MASK (0xFFFF << 16) + #define EQOS_RDES3_OWN (1U << 31) #define EQOS_RDES3_IOC (1U << 30) @@ -292,4 +345,5 @@ #define EQOS_RDES3_RE (1U << 20) #define EQOS_RDES3_LENGTH_MASK 0x7FFFU + #endif diff --git a/sys/dev/eqos/if_eqos_var.h b/sys/dev/eqos/if_eqos_var.h index c21a703747ec..1f6cd2f63eb1 100644 --- a/sys/dev/eqos/if_eqos_var.h +++ b/sys/dev/eqos/if_eqos_var.h @@ -76,20 +76,29 @@ struct eqos_softc { struct resource *res[EQOS_RES_COUNT]; void *irq_handle; #ifdef FDT - struct syscon *grf; + struct syscon *grf, *php_grf; int grf_offset; + int phy_mode; + struct eqos_ops *ops; + clk_t *clks; + clk_t clk_stmmaceth; + bool clock_in; + uint8_t idx; + uint8_t axi_rd_osr_lmt, axi_wr_osr_lmt; + uint16_t axi_blen[AXI_BLEN]; #endif uint32_t csr_clock; uint32_t csr_clock_range; uint32_t hw_feature[4]; bool link_up; int tx_watchdog; - + uint8_t force_thresh_dma_mode; + struct ifnet *ifp; device_t miibus; struct mtx lock; - struct callout callout; - + struct callout callout; + struct callout calltxi; struct eqos_ring tx; struct eqos_ring rx; }; diff --git a/sys/dev/extres/clk/clk.c b/sys/dev/extres/clk/clk.c index c569b05b6189..3d4ede27796a 100644 --- a/sys/dev/extres/clk/clk.c +++ b/sys/dev/extres/clk/clk.c @@ -962,12 +962,13 @@ clknode_get_freq(struct clknode *clknode, uint64_t *freq) CLKNODE_UNLOCK(clknode); return (0); } +#define CLK_SET_NOTBUSY 0x00020000 static int _clknode_set_freq(struct clknode *clknode, uint64_t *freq, int flags, int enablecnt) { - int rv, done; + int rv = 0, done; uint64_t parent_freq; /* We have exclusive topology lock, node lock is not needed. */ @@ -975,7 +976,7 @@ _clknode_set_freq(struct clknode *clknode, uint64_t *freq, int flags, /* Check for no change */ if (clknode->freq == *freq) - return (0); + goto out; parent_freq = 0; @@ -985,18 +986,19 @@ _clknode_set_freq(struct clknode *clknode, uint64_t *freq, int flags, * OR * clock is glitch free and is enabled by calling consumer only */ - if ((flags & CLK_SET_DRYRUN) == 0 && + if (((flags & CLK_SET_DRYRUN) == 0 || (flags & CLK_SET_NOTBUSY)) && clknode->enable_cnt > 1 && clknode->enable_cnt > enablecnt && (clknode->flags & CLK_NODE_GLITCH_FREE) == 0) { - return (EBUSY); + rv = EBUSY; + goto out; } /* Get frequency from parent, if the clock has a parent. */ if (clknode->parent_cnt > 0) { rv = clknode_get_freq(clknode->parent, &parent_freq); if (rv != 0) { - return (rv); + goto out; } } @@ -1007,7 +1009,7 @@ _clknode_set_freq(struct clknode *clknode, uint64_t *freq, int flags, clknode->name, rv); if ((flags & CLK_SET_DRYRUN) == 0) clknode_refresh_cache(clknode, parent_freq); - return (rv); + goto out; } if (done) { @@ -1019,7 +1021,7 @@ _clknode_set_freq(struct clknode *clknode, uint64_t *freq, int flags, rv = clknode_get_freq(clknode->parent, &parent_freq); if (rv != 0) { - return (rv); + goto out; } } clknode_refresh_cache(clknode, parent_freq); @@ -1034,7 +1036,10 @@ _clknode_set_freq(struct clknode *clknode, uint64_t *freq, int flags, clknode->name); rv = ENXIO; } - +out: +#ifdef CLK_DEBUG + printf("CLOCK SET: %s set to %ju => %d\n", clknode_get_name(clknode), *freq, rv); +#endif return (rv); } diff --git a/sys/dev/firmware/arm/scmi.c b/sys/dev/firmware/arm/scmi.c index ee1d2a31adba..4bb4704b0b35 100644 --- a/sys/dev/firmware/arm/scmi.c +++ b/sys/dev/firmware/arm/scmi.c @@ -44,10 +44,15 @@ #include #include "dev/mailbox/arm/arm_doorbell.h" +#include "dev/psci/psci.h" #include "scmi.h" #include "scmi_protocols.h" +enum scmi_transport { + SCMI_SMC = 1, + SCMI_MBOX, +}; struct scmi_softc { struct simplebus_softc simplebus_sc; device_t dev; @@ -55,6 +60,8 @@ struct scmi_softc { struct arm_doorbell *db; struct mtx mtx; int req_done; + uint32_t smc_id; + uint8_t ttype; }; static device_t @@ -110,7 +117,7 @@ static int scmi_request_locked(struct scmi_softc *sc, struct scmi_req *req) { struct scmi_smt_header hdr; - int timeout; + int timeout, status; bzero(&hdr, sizeof(struct scmi_smt_header)); @@ -127,7 +134,8 @@ scmi_request_locked(struct scmi_softc *sc, struct scmi_req *req) hdr.msg_header = req->protocol_id << SMT_HEADER_PROTOCOL_ID_S; hdr.msg_header |= req->message_id << SMT_HEADER_MESSAGE_ID_S; hdr.length = sizeof(hdr.msg_header) + req->in_size; - hdr.flags |= SCMI_SHMEM_FLAG_INTR_ENABLED; + if(sc->ttype == SCMI_MBOX) + hdr.flags |= SCMI_SHMEM_FLAG_INTR_ENABLED; /* Write header */ scmi_shmem_write(sc->tx_shmem, 0, &hdr, SMT_HEADER_SIZE); @@ -136,39 +144,43 @@ scmi_request_locked(struct scmi_softc *sc, struct scmi_req *req) scmi_shmem_write(sc->tx_shmem, SMT_HEADER_SIZE, req->in_buf, req->in_size); - sc->req_done = 0; - - /* Interrupt SCP firmware. */ - arm_doorbell_set(sc->db); - - timeout = 200; - - dprintf("%s: request\n", __func__); - - do { - if (cold) { - if (arm_doorbell_get(sc->db)) - break; - DELAY(10000); - } else { - msleep(sc, &sc->mtx, 0, "scmi", hz / 10); - if (sc->req_done) - break; - } - } while (timeout--); - - if (timeout <= 0) - return (-1); - - dprintf("%s: got reply, timeout %d\n", __func__, timeout); - + if(sc->ttype == SCMI_MBOX) { + sc->req_done = 0; + + /* Interrupt SCP firmware. */ + arm_doorbell_set(sc->db); + + timeout = 200; + dprintf("%s: request\n", __func__); + + do { + if (cold) { + if (arm_doorbell_get(sc->db)) + break; + DELAY(10000); + } else { + msleep(sc, &sc->mtx, 0, "scmi", hz / 10); + if (sc->req_done) + break; + } + } while (timeout--); + + if (timeout <= 0) + return (-1); + + dprintf("%s: got reply, timeout %d\n", __func__, timeout); + } else { + status = psci_call(sc->smc_id, 0, 0, 0); + if(status) + return (status); + } /* Read header. */ scmi_shmem_read(sc->tx_shmem, 0, &hdr, SMT_HEADER_SIZE); /* Read response */ scmi_shmem_read(sc->tx_shmem, SMT_HEADER_SIZE, req->out_buf, req->out_size); - +/* printf("TRALALA :%08x\n",hdr.channel_status);*/ return (0); } @@ -187,12 +199,17 @@ scmi_request(device_t dev, struct scmi_req *req) return (error); } + +static struct ofw_compat_data compat_data[] = { + {"arm,scmi", SCMI_MBOX}, + {"arm,scmi-smc", SCMI_SMC}, + {NULL, 0} +}; static int scmi_probe(device_t dev) { - - if (!ofw_bus_is_compatible(dev, "arm,scmi")) - return (ENXIO); + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); if (!ofw_bus_status_okay(dev)) return (ENXIO); @@ -208,10 +225,9 @@ scmi_attach(device_t dev) struct scmi_softc *sc; phandle_t node; int error; - sc = device_get_softc(dev); sc->dev = dev; - + sc->ttype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; node = ofw_bus_get_node(dev); if (node == -1) return (ENXIO); @@ -222,16 +238,22 @@ scmi_attach(device_t dev) return (ENXIO); } - sc->db = arm_doorbell_ofw_get(sc->dev, "tx"); - if (sc->db == NULL) { - device_printf(dev, "Doorbell device not found.\n"); - return (ENXIO); + if(sc->ttype == SCMI_MBOX) { + sc->db = arm_doorbell_ofw_get(sc->dev, "tx"); + if (sc->db == NULL) { + device_printf(dev, "Doorbell device not found.\n"); + return (ENXIO); + } + + arm_doorbell_set_handler(sc->db, scmi_callback, sc); + } else { + if(OF_getencprop(node, "arm,smc-id", &sc->smc_id, sizeof(sc->smc_id)) <= 0) { + device_printf(dev, "arm,smc-id not found.\n"); + return (ENXIO); + } } mtx_init(&sc->mtx, device_get_nameunit(dev), "SCMI", MTX_DEF); - - arm_doorbell_set_handler(sc->db, scmi_callback, sc); - simplebus_init(dev, node); /* @@ -267,5 +289,5 @@ static device_method_t scmi_methods[] = { DEFINE_CLASS_1(scmi, scmi_driver, scmi_methods, sizeof(struct scmi_softc), simplebus_driver); -DRIVER_MODULE(scmi, simplebus, scmi_driver, 0, 0); +EARLY_DRIVER_MODULE(scmi, simplebus, scmi_driver, 0, 0, BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_LATE); MODULE_VERSION(scmi, 1); diff --git a/sys/dev/firmware/arm/scmi_clk.c b/sys/dev/firmware/arm/scmi_clk.c index 30d630c8ef57..bc12022774c0 100644 --- a/sys/dev/firmware/arm/scmi_clk.c +++ b/sys/dev/firmware/arm/scmi_clk.c @@ -155,8 +155,17 @@ scmi_clknode_init(struct clknode *clk, device_t dev) static int scmi_clknode_recalc_freq(struct clknode *clk, uint64_t *freq) { + struct scmi_clknode_softc *clk_sc; + struct scmi_clk_softc *sc; + int error; - return (0); + clk_sc = clknode_get_softc(clk); + sc = device_get_softc(clk_sc->dev); + + error = scmi_clk_get_rate(sc, clk_sc->clock_id, freq); + dprintf("%s: %ld\n", __func__, *freq); + + return (error); } static int diff --git a/sys/dev/flash/mx25l.c b/sys/dev/flash/mx25l.c index 64e3e53d4291..8fe2eef250ff 100644 --- a/sys/dev/flash/mx25l.c +++ b/sys/dev/flash/mx25l.c @@ -122,6 +122,7 @@ static struct mx25l_flash_ident flash_devices[] = { { "en25q64", 0x1c, 0x3017, 64 * 1024, 128, FL_ERASE_4K }, { "m25p32", 0x20, 0x2016, 64 * 1024, 64, FL_NONE }, { "m25p64", 0x20, 0x2017, 64 * 1024, 128, FL_NONE }, + { "xm25qu128c", 0x20, 0x4118, 64 * 1024, 256, FL_ERASE_4K | FL_ERASE_32K }, { "mx25l1606e", 0xc2, 0x2015, 64 * 1024, 32, FL_ERASE_4K}, { "mx25ll32", 0xc2, 0x2016, 64 * 1024, 64, FL_NONE }, { "mx25ll64", 0xc2, 0x2017, 64 * 1024, 128, FL_NONE }, @@ -154,6 +155,14 @@ static struct mx25l_flash_ident flash_devices[] = { /* Integrated Silicon Solution */ { "is25wp256", 0x9d, 0x7019, 64 * 1024, 512, FL_ERASE_4K | FL_ENABLE_4B_ADDR}, + + /* XTX (Shenzhen Xin Tian Xia Tech) */ + { "xt25f32b", 0x0b, 0x4016, 64 * 1024, 64, FL_ERASE_4K }, + { "xt25f128b", 0x0b, 0x4018, 64 * 1024, 256, FL_ERASE_4K }, + + /* zbit */ + { "zb25vq128", 0x5e, 0x4018, 64 * 1024, 256, FL_ERASE_4K }, + }; static int diff --git a/sys/dev/mmc/host/dwmmc.c b/sys/dev/mmc/host/dwmmc.c index 53c3e0b646fe..217ac64b13be 100644 --- a/sys/dev/mmc/host/dwmmc.c +++ b/sys/dev/mmc/host/dwmmc.c @@ -50,8 +50,8 @@ #include #include -#include +#include #include #include #include @@ -480,8 +480,12 @@ dwmmc_card_task(void *arg, int pending __unused) #else DWMMC_LOCK(sc); +#ifdef FDT if (READ4(sc, SDMMC_CDETECT) == 0 || (sc->mmc_helper.props & MMC_PROP_BROKEN_CD)) { +#else + if (READ4(sc, SDMMC_CDETECT) == 0) { +#endif if (sc->child == NULL) { if (bootverbose) device_printf(sc->dev, "Card inserted\n"); @@ -509,6 +513,7 @@ dwmmc_card_task(void *arg, int pending __unused) #endif /* MMCCAM */ } +#ifdef FDT static int parse_fdt(struct dwmmc_softc *sc) { @@ -665,6 +670,7 @@ parse_fdt(struct dwmmc_softc *sc) fail: return (ENXIO); } +#endif int dwmmc_attach(device_t dev) @@ -679,12 +685,14 @@ dwmmc_attach(device_t dev) /* Why not to use Auto Stop? It save a hundred of irq per second */ sc->use_auto_stop = 1; - error = parse_fdt(sc); - if (error != 0) { - device_printf(dev, "Can't get FDT property.\n"); +#ifdef FDT + parse_fdt(sc); +#else + if (!sc->bus_hz) { + device_printf(dev, "Can't get device properties\n"); return (ENXIO); } - +#endif DWMMC_LOCK_INIT(sc); if (bus_alloc_resources(dev, dwmmc_spec, sc->res)) { @@ -893,7 +901,9 @@ dwmmc_update_ios(device_t brdev, device_t reqdev) break; } +#ifdef FDT mmc_fdt_set_power(&sc->mmc_helper, ios->power_mode); +#endif if (ios->bus_width == bus_width_8) WRITE4(sc, SDMMC_CTYPE, SDMMC_CTYPE_8BIT); diff --git a/sys/dev/mmc/host/dwmmc_var.h b/sys/dev/mmc/host/dwmmc_var.h index ef9b1d5305bd..d0012c7d5f99 100644 --- a/sys/dev/mmc/host/dwmmc_var.h +++ b/sys/dev/mmc/host/dwmmc_var.h @@ -52,7 +52,9 @@ struct dwmmc_softc { device_t dev; void *intr_cookie; struct mmc_host host; +#ifdef FDT struct mmc_helper mmc_helper; +#endif struct mtx sc_mtx; #ifdef MMCCAM union ccb * ccb; diff --git a/sys/dev/sdhci/sdhci.c b/sys/dev/sdhci/sdhci.c index 3dc8fb617820..3b54c4cfb65e 100644 --- a/sys/dev/sdhci/sdhci.c +++ b/sys/dev/sdhci/sdhci.c @@ -226,6 +226,9 @@ slot_sprintf(const struct sdhci_slot *slot, struct sbuf *s, static void sdhci_dumpregs_buf(struct sdhci_slot *slot, struct sbuf *s) { + + if (bootverbose || sdhci_debug) { + slot_sprintf(slot, s, "============== REGISTER DUMP ==============\n"); slot_sprintf(slot, s, "Sys addr: 0x%08x | Version: 0x%08x\n", @@ -254,6 +257,7 @@ sdhci_dumpregs_buf(struct sdhci_slot *slot, struct sbuf *s) RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS)); slot_sprintf(slot, s, "===========================================\n"); + } } static void @@ -417,7 +421,8 @@ sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) if (clock == slot->clock) return; - clock = SDHCI_SET_CLOCK(slot->bus, slot, clock); + + /* clock = SDHCI_SET_CLOCK(slot->bus, slot, clock);*/ slot->clock = clock; /* Turn off the clock. */ @@ -474,7 +479,6 @@ sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) } div >>= 1; } - if (bootverbose || sdhci_debug) slot_printf(slot, "Divider %d for freq %d (base %d)\n", div, clock, clk_base); @@ -504,6 +508,7 @@ sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) /* Pass clock signal to the bus. */ clk |= SDHCI_CLOCK_CARD_EN; WR2(slot, SDHCI_CLOCK_CONTROL, clk); + clock = SDHCI_SET_CLOCK(slot->bus, slot, clock); } static void @@ -2203,10 +2208,10 @@ sdhci_generic_release_host(device_t brdev __unused, device_t reqdev) static void sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) { - if (!slot->curcmd) { - slot_printf(slot, "Got command interrupt 0x%08x, but " - "there is no active command.\n", intmask); + if (bootverbose || sdhci_debug) + slot_printf(slot, "Got command interrupt 0x%08x, but " + "there is no active command.\n", intmask); sdhci_dumpregs(slot); return; } @@ -2228,8 +2233,9 @@ sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) uint32_t sdma_bbufsz; if (!slot->curcmd) { - slot_printf(slot, "Got data interrupt 0x%08x, but " - "there is no active command.\n", intmask); + if (bootverbose || sdhci_debug) + slot_printf(slot, "Got data interrupt 0x%08x, but " + "there is no active command.\n", intmask); sdhci_dumpregs(slot); return; } @@ -2339,8 +2345,9 @@ sdhci_acmd_irq(struct sdhci_slot *slot, uint16_t acmd_err) { if (!slot->curcmd) { - slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " - "there is no active command.\n", acmd_err); + if (bootverbose || sdhci_debug) + slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " + "there is no active command.\n", acmd_err); sdhci_dumpregs(slot); return; } diff --git a/sys/dev/sdhci/sdhci.h b/sys/dev/sdhci/sdhci.h index c5b2f24061ae..78f34b0969f3 100644 --- a/sys/dev/sdhci/sdhci.h +++ b/sys/dev/sdhci/sdhci.h @@ -408,6 +408,8 @@ struct sdhci_slot { #define SDHCI_USE_DMA 4 /* Use DMA for this req. */ #define PLATFORM_DATA_STARTED 8 /* Data xfer is handled by platform */ + int (*vendor_clock)(struct sdhci_slot *, int); + #ifdef MMCCAM /* CAM stuff */ union ccb *ccb; diff --git a/sys/dev/sdhci/sdhci_acpi.c b/sys/dev/sdhci/sdhci_acpi.c index 80c58901b9a0..9a1e3eeea358 100644 --- a/sys/dev/sdhci/sdhci_acpi.c +++ b/sys/dev/sdhci/sdhci_acpi.c @@ -52,6 +52,8 @@ #define SDHCI_AMD_RESET_DLL_REG 0x908 +#define RK3568 1 /* serg */ + static const struct sdhci_acpi_device { const char* hid; int uid; @@ -83,6 +85,12 @@ static const struct sdhci_acpi_device { { "AMDI0040", 0, "AMD eMMC 5.0 Controller", SDHCI_QUIRK_32BIT_DMA_SIZE | SDHCI_QUIRK_MMC_HS400_IF_CAN_SDR104 }, +#if RK3568 /* serg */ + { "RKCP0D40", 0, "Rockchip eMMC Controller", + SDHCI_QUIRK_MMC_DDR52 | + SDHCI_QUIRK_32BIT_DMA_SIZE | + SDHCI_QUIRK_PRESET_VALUE_BROKEN }, +#endif { NULL, 0, NULL, 0} }; @@ -92,9 +100,33 @@ static char *sdhci_ids[] = { "80865ACA", "80865ACC", "AMDI0040", +#if RK3568 /* serg */ + "RKCP0D40", +#endif NULL }; +#if RK3568 /* serg */ + /* 434addb0-8ff3-49d5-a724-95844b79ad1f */ + /* ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), rk3588 */ +static uint8_t rk_dsm_uuid[ACPI_UUID_LENGTH] = { + 0xb0, 0xdd, 0x4a, 0x43, 0xf3, 0x8f, 0xd5, 0x49, + 0xa7, 0x24, 0x95, 0x84, 0x4b, 0x79, 0xad, 0x1f +}; +#endif + +/* +Set Card Clock +The _DSM control method parameters for +the Set Card Clock function are as follows: + +Arguments +Arg0: UUID = 434addb0-8ff3-49d5-a724-95844b79ad1f +Arg1: Revision = 0 +Arg2: Function Index = 1 +Arg3: Target card clock rate in Hz. +*/ + struct sdhci_acpi_softc { struct sdhci_slot slot; struct resource *mem_res; /* Memory resource */ @@ -266,6 +298,48 @@ sdhci_acpi_find_device(device_t dev) return (NULL); } +#if RK3568 /* serg */ +static int +sdhci_acpi_setclock(struct sdhci_slot *slot, int clock) +{ + ACPI_HANDLE handle; + ACPI_STATUS rv; + ACPI_OBJECT frequency; + ACPI_OBJECT function; + ACPI_BUFFER buf; + + device_printf(slot->dev, "Set clock via DSM enter\n" ); /* serg */ + + if (!(handle = acpi_get_handle(device_get_parent(slot->dev)))) { + device_printf(slot->dev, "ACPI handle is NULL\n"); + return (ENXIO); + } + + frequency.Integer.Type = ACPI_TYPE_INTEGER; + frequency.Integer.Value = clock; + function.Package.Type = ACPI_TYPE_PACKAGE; + function.Package.Count = 1; + function.Package.Elements = &frequency; + + rv = acpi_EvaluateDSMTyped(handle, rk_dsm_uuid, 0, 1, &function, &buf, ACPI_TYPE_INTEGER); + + if (ACPI_FAILURE(rv)) { + device_printf(slot->dev, "Set clock via DSM failed: %s\n", + AcpiFormatException(rv)); + return (ENXIO); + } + + if (buf.Pointer) { + //ACPI_OBJECT *result = (ACPI_OBJECT *)buf.Pointer; + //device_printf(slot->dev, "Set clock via DSM returned %ld Hz\n", + // result->Integer.Value); + AcpiOsFree(buf.Pointer); + } + + return (0); +} +#endif + static int sdhci_acpi_probe(device_t dev) { @@ -326,6 +400,17 @@ sdhci_acpi_attach(device_t dev) quirks |= sdhci_quirk_set; sc->slot.quirks = quirks; +#if RK3568 /* serg */ + if (!strcmp(acpi_dev->hid, "RKCP0D40")) { + if (acpi_DSMQuery(acpi_get_handle(dev), rk_dsm_uuid, 0) & 0x0001) { + device_printf(dev, "RK356x vendor_clock enabled\n"); + sc->slot.vendor_clock = sdhci_acpi_setclock; + } + else + device_printf(dev, "RK356x vendor_clock failed\n"); + } +#endif + err = sdhci_init_slot(dev, &sc->slot, 0); if (err) { device_printf(dev, "failed to init slot\n"); diff --git a/sys/dev/sdhci/sdhci_fdt.c b/sys/dev/sdhci/sdhci_fdt.c index 4a355d6514ad..b92e7b698898 100644 --- a/sys/dev/sdhci/sdhci_fdt.c +++ b/sys/dev/sdhci/sdhci_fdt.c @@ -70,12 +70,11 @@ #define MAX_SLOTS 6 #define SDHCI_FDT_ARMADA38X 1 -#define SDHCI_FDT_GENERIC 2 -#define SDHCI_FDT_XLNX_ZY7 3 -#define SDHCI_FDT_QUALCOMM 4 -#define SDHCI_FDT_RK3399 5 -#define SDHCI_FDT_RK3568 6 -#define SDHCI_FDT_XLNX_ZMP 7 +#define SDHCI_FDT_XLNX_ZY7 2 +#define SDHCI_FDT_QUALCOMM 3 +#define SDHCI_FDT_RK3399 4 +#define SDHCI_FDT_RK3568 5 +#define SDHCI_FDT_XLNX_ZMP 6 #define RK3399_GRF_EMMCCORE_CON0 0xf000 #define RK3399_CORECFG_BASECLKFREQ 0xff00 @@ -84,14 +83,16 @@ #define RK3399_GRF_EMMCCORE_CON11 0xf02c #define RK3399_CORECFG_CLOCKMULTIPLIER 0xff +#define RK35XX_CTRL_HS400 0x7 #define RK3568_EMMC_HOST_CTRL 0x0508 #define RK3568_EMMC_EMMC_CTRL 0x052c +#define RK35XX_CARD_IS_EMMC 0x1 #define RK3568_EMMC_ATCTRL 0x0540 #define RK3568_EMMC_DLL_CTRL 0x0800 -#define DLL_CTRL_SRST 0x00000001 -#define DLL_CTRL_START 0x00000002 +#define DLL_CTRL_START 0x00000001 #define DLL_CTRL_START_POINT_DEFAULT 0x00050000 #define DLL_CTRL_INCREMENT_DEFAULT 0x00000200 +#define DLL_CTRL_BYPASS 0x01000000 #define RK3568_EMMC_DLL_RXCLK 0x0804 #define DLL_RXCLK_DELAY_ENABLE 0x08000000 @@ -99,13 +100,18 @@ #define RK3568_EMMC_DLL_TXCLK 0x0808 #define DLL_TXCLK_DELAY_ENABLE 0x08000000 -#define DLL_TXCLK_TAPNUM_DEFAULT 0x00000008 +#define DLL_TXCLK_TAPNUM_DEFAULT 0x00000010 #define DLL_TXCLK_TAPNUM_FROM_SW 0x01000000 #define RK3568_EMMC_DLL_STRBIN 0x080c #define DLL_STRBIN_DELAY_ENABLE 0x08000000 #define DLL_STRBIN_TAPNUM_DEFAULT 0x00000008 -#define DLL_STRBIN_TAPNUM_FROM_SW 0x01000000 +#define DLL_STRBIN_DELAY_NUM_SEL 0x04000000 +#define DLL_STRBIN_DELAY_NUM_OFFSET 16 +#define DLL_STRBIN_DELAY_NUM_DEFAULT 0x16 +#define DLL_STRBIN_TAPNUM_FROM_SW 0x01000000 + +#define RK3568_EMMC_DLL_CMDOUT 0x0810 #define RK3568_EMMC_DLL_STATUS0 0x0840 #define DLL_STATUS0_DLL_LOCK 0x00000100 @@ -114,15 +120,13 @@ #define LOWEST_SET_BIT(mask) ((((mask) - 1) & (mask)) ^ (mask)) #define SHIFTIN(x, mask) ((x) * LOWEST_SET_BIT(mask)) -#define EMMCCARDCLK_ID 1000 - static struct ofw_compat_data compat_data[] = { { "marvell,armada-380-sdhci", SDHCI_FDT_ARMADA38X }, - { "sdhci_generic", SDHCI_FDT_GENERIC }, { "qcom,sdhci-msm-v4", SDHCI_FDT_QUALCOMM }, { "rockchip,rk3399-sdhci-5.1", SDHCI_FDT_RK3399 }, { "xlnx,zy7_sdhci", SDHCI_FDT_XLNX_ZY7 }, { "rockchip,rk3568-dwcmshc", SDHCI_FDT_RK3568 }, + { "rockchip,rk3588-dwcmshc", SDHCI_FDT_RK3568 }, { "xlnx,zynqmp-8.9a", SDHCI_FDT_XLNX_ZMP }, { NULL, 0 } }; @@ -148,39 +152,40 @@ struct sdhci_fdt_softc { clk_t clk_ahb; /* ahb clock */ clk_t clk_core; /* core clock */ phy_t phy; /* phy to be used */ + + struct syscon *syscon; /* Handle to the syscon */ }; -struct rk3399_emmccardclk_sc { +struct sdhci_exported_clocks_sc { device_t clkdev; - bus_addr_t reg; }; static int -rk3399_emmccardclk_init(struct clknode *clk, device_t dev) +sdhci_exported_clocks_init(struct clknode *clk, device_t dev) { clknode_init_parent_idx(clk, 0); return (0); } -static clknode_method_t rk3399_emmccardclk_clknode_methods[] = { +static clknode_method_t sdhci_exported_clocks_clknode_methods[] = { /* Device interface */ - CLKNODEMETHOD(clknode_init, rk3399_emmccardclk_init), + CLKNODEMETHOD(clknode_init, sdhci_exported_clocks_init), CLKNODEMETHOD_END }; -DEFINE_CLASS_1(rk3399_emmccardclk_clknode, rk3399_emmccardclk_clknode_class, - rk3399_emmccardclk_clknode_methods, sizeof(struct rk3399_emmccardclk_sc), +DEFINE_CLASS_1(sdhci_exported_clocks_clknode, sdhci_exported_clocks_clknode_class, + sdhci_exported_clocks_clknode_methods, sizeof(struct sdhci_exported_clocks_sc), clknode_class); static int -rk3399_ofw_map(struct clkdom *clkdom, uint32_t ncells, +sdhci_clock_ofw_map(struct clkdom *clkdom, uint32_t ncells, phandle_t *cells, struct clknode **clk) { + int id = 1; /* Our clock id starts at 1 */ - if (ncells == 0) - *clk = clknode_find_by_id(clkdom, EMMCCARDCLK_ID); - else - return (ERANGE); + if (ncells != 0) + id = cells[1]; + *clk = clknode_find_by_id(clkdom, id); if (*clk == NULL) return (ENXIO); @@ -188,30 +193,29 @@ rk3399_ofw_map(struct clkdom *clkdom, uint32_t ncells, } static void -sdhci_init_rk3399_emmccardclk(device_t dev) +sdhci_export_clocks(struct sdhci_fdt_softc *sc) { struct clknode_init_def def; - struct rk3399_emmccardclk_sc *sc; + struct sdhci_exported_clocks_sc *clksc; struct clkdom *clkdom; struct clknode *clk; - clk_t clk_parent; bus_addr_t paddr; bus_size_t psize; const char **clknames; phandle_t node; int i, nclocks, ncells, error; - node = ofw_bus_get_node(dev); + node = ofw_bus_get_node(sc->dev); if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) { - device_printf(dev, "cannot parse 'reg' property\n"); + device_printf(sc->dev, "cannot parse 'reg' property\n"); return; } error = ofw_bus_parse_xref_list_get_length(node, "clocks", "#clock-cells", &ncells); if (error != 0 || ncells != 2) { - device_printf(dev, "couldn't find parent clocks\n"); + device_printf(sc->dev, "couldn't find parent clocks\n"); return; } @@ -221,47 +225,31 @@ sdhci_init_rk3399_emmccardclk(device_t dev) if (nclocks <= 0) return; - if (nclocks != 1) { - device_printf(dev, "Having %d clock instead of 1, aborting\n", - nclocks); - return; - } + clkdom = clkdom_create(sc->dev); + clkdom_set_ofw_mapper(clkdom, sdhci_clock_ofw_map); + + for (i = 0; i < nclocks; i++) { + memset(&def, 0, sizeof(def)); + def.id = i + 1; /* Exported clock IDs starts at 1 */ + def.name = clknames[i]; + def.parent_names = malloc(sizeof(char *) * 1, M_OFWPROP, M_WAITOK); + def.parent_names[0] = clk_get_name(sc->clk_xin); + def.parent_cnt = 1; - clkdom = clkdom_create(dev); - clkdom_set_ofw_mapper(clkdom, rk3399_ofw_map); - - memset(&def, 0, sizeof(def)); - def.id = EMMCCARDCLK_ID; - def.name = clknames[0]; - def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK); - for (i = 0; i < ncells; i++) { - error = clk_get_by_ofw_index(dev, 0, i, &clk_parent); - if (error != 0) { - device_printf(dev, "cannot get clock %d\n", error); + clk = clknode_create(clkdom, &sdhci_exported_clocks_clknode_class, &def); + if (clk == NULL) { + device_printf(sc->dev, "cannot create clknode\n"); return; } - def.parent_names[i] = clk_get_name(clk_parent); - if (bootverbose) - device_printf(dev, "clk parent: %s\n", - def.parent_names[i]); - clk_release(clk_parent); - } - def.parent_cnt = ncells; - - clk = clknode_create(clkdom, &rk3399_emmccardclk_clknode_class, &def); - if (clk == NULL) { - device_printf(dev, "cannot create clknode\n"); - return; - } - sc = clknode_get_softc(clk); - sc->reg = paddr; - sc->clkdev = device_get_parent(dev); + clksc = clknode_get_softc(clk); + clksc->clkdev = device_get_parent(sc->dev); - clknode_register(clkdom, clk); + clknode_register(clkdom, clk); + } if (clkdom_finit(clkdom) != 0) { - device_printf(dev, "cannot finalize clkdom initialization\n"); + device_printf(sc->dev, "cannot finalize clkdom initialization\n"); return; } @@ -270,13 +258,9 @@ sdhci_init_rk3399_emmccardclk(device_t dev) } static int -sdhci_init_rk3399(device_t dev) +sdhci_init_clocks(device_t dev) { struct sdhci_fdt_softc *sc = device_get_softc(dev); - struct syscon *grf = NULL; - phandle_t node; - uint64_t freq; - uint32_t mask, val; int error; /* Get and activate clocks */ @@ -290,11 +274,6 @@ sdhci_init_rk3399(device_t dev) device_printf(dev, "cannot enable xin clock\n"); return (ENXIO); } - error = clk_get_freq(sc->clk_xin, &freq); - if (error != 0) { - device_printf(dev, "cannot get xin clock frequency\n"); - return (ENXIO); - } error = clk_get_by_ofw_name(dev, 0, "clk_ahb", &sc->clk_ahb); if (error != 0) { device_printf(dev, "cannot get ahb clock\n"); @@ -306,43 +285,106 @@ sdhci_init_rk3399(device_t dev) return (ENXIO); } - /* Register clock */ - sdhci_init_rk3399_emmccardclk(dev); + return (0); +} + +static int +sdhci_init_phy(struct sdhci_fdt_softc *sc) +{ + int error; /* Enable PHY */ - error = phy_get_by_ofw_name(dev, 0, "phy_arasan", &sc->phy); + error = phy_get_by_ofw_name(sc->dev, 0, "phy_arasan", &sc->phy); + if (error == ENOENT) + return (0); if (error != 0) { - device_printf(dev, "Could not get phy\n"); + device_printf(sc->dev, "Could not get phy\n"); return (ENXIO); } error = phy_enable(sc->phy); if (error != 0) { - device_printf(dev, "Could not enable phy\n"); + device_printf(sc->dev, "Could not enable phy\n"); return (ENXIO); } + + return (0); +} + +static int +sdhci_get_syscon(struct sdhci_fdt_softc *sc) +{ + phandle_t node; + /* Get syscon */ - node = ofw_bus_get_node(dev); + node = ofw_bus_get_node(sc->dev); if (OF_hasprop(node, "arasan,soc-ctl-syscon") && - syscon_get_by_ofw_property(dev, node, - "arasan,soc-ctl-syscon", &grf) != 0) { - device_printf(dev, "cannot get grf driver handle\n"); + syscon_get_by_ofw_property(sc->dev, node, + "arasan,soc-ctl-syscon", &sc->syscon) != 0) { + device_printf(sc->dev, "cannot get syscon handle\n"); + return (ENXIO); + } + + return (0); +} + +static int +sdhci_init_rk3399(device_t dev) +{ + struct sdhci_fdt_softc *sc = device_get_softc(dev); + uint64_t freq; + uint32_t mask, val; + int error; + + error = clk_get_freq(sc->clk_xin, &freq); + if (error != 0) { + device_printf(dev, "cannot get xin clock frequency\n"); return (ENXIO); } /* Disable clock multiplier */ mask = RK3399_CORECFG_CLOCKMULTIPLIER; val = 0; - SYSCON_WRITE_4(grf, RK3399_GRF_EMMCCORE_CON11, (mask << 16) | val); + SYSCON_WRITE_4(sc->syscon, RK3399_GRF_EMMCCORE_CON11, (mask << 16) | val); /* Set base clock frequency */ mask = RK3399_CORECFG_BASECLKFREQ; val = SHIFTIN((freq + (1000000 / 2)) / 1000000, RK3399_CORECFG_BASECLKFREQ); - SYSCON_WRITE_4(grf, RK3399_GRF_EMMCCORE_CON0, (mask << 16) | val); + SYSCON_WRITE_4(sc->syscon, RK3399_GRF_EMMCCORE_CON0, (mask << 16) | val); return (0); } +static int +sdhci_init_rk3568(device_t dev) +{ + struct sdhci_fdt_softc *sc = device_get_softc(dev); + int err, i; + char *rk35xx_clocks[] = {"bus", "timer", "axi", "block" }; + + /* setup & enable clocks */ + if (clk_get_by_ofw_name(dev, 0, "core", &sc->clk_core)) { + device_printf(dev, "cannot get core clock\n"); + return (ENXIO); + } + err = clk_enable(sc->clk_core); + if(err) + device_printf(dev, "cannot enable core clock\n"); + return (err); + for(i = 0; i < nitems(rk35xx_clocks);i++) { + clk_t clk_tmp; + if (clk_get_by_ofw_name(dev, 0,rk35xx_clocks[i], &clk_tmp)) { + device_printf(dev, "cannot get %s clock\n", rk35xx_clocks[i]); + return (ENXIO); + } + err = clk_enable(clk_tmp); + if(err) + break; + } + + return (err); +} + static uint8_t sdhci_fdt_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) { @@ -437,30 +479,86 @@ sdhci_fdt_get_ro(device_t bus, device_t dev) return (sdhci_generic_get_ro(bus, dev) ^ sc->wp_inverted); } +static void +rk35xx_set_uhs_timing(device_t brdev, struct sdhci_slot *slot) +{ + uint16_t ctrl, ctrl_2; + const struct mmc_ios *ios; + + if (slot->version < SDHCI_SPEC_300) return; + + mtx_assert(&slot->mtx, MA_OWNED); + ios = &slot->host.ios; + + ctrl_2 = sdhci_fdt_read_2(brdev, slot, SDHCI_HOST_CONTROL2); + /* Select Bus Speed Mode for host */ + ctrl_2 &= ~SDHCI_CTRL2_UHS_MASK; + + if ((ios->timing == bus_timing_mmc_hs200) || + (ios->timing == bus_timing_uhs_sdr104)) + ctrl_2 |= SDHCI_CTRL2_UHS_SDR104; + else if (ios->timing == bus_timing_uhs_sdr12) + ctrl_2 |= SDHCI_CTRL2_UHS_SDR12; + else if ((ios->timing == bus_timing_uhs_sdr25)) + ctrl_2 |= SDHCI_CTRL2_UHS_SDR25; + else if (ios->timing == bus_timing_uhs_sdr50) + ctrl_2 |= SDHCI_CTRL2_UHS_SDR50; + else if ((ios->timing == bus_timing_uhs_ddr50) || + (ios->timing == bus_timing_mmc_ddr52)) + ctrl_2 |= SDHCI_CTRL2_UHS_DDR50; + else if (ios->timing == bus_timing_mmc_hs400) { + /* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */ + ctrl = sdhci_fdt_read_2(brdev, slot, RK3568_EMMC_EMMC_CTRL); + ctrl |= RK35XX_CARD_IS_EMMC; + sdhci_fdt_write_2(brdev, slot, RK3568_EMMC_EMMC_CTRL, ctrl); + ctrl_2 |= RK35XX_CTRL_HS400; + } + + sdhci_fdt_write_2(brdev, slot, SDHCI_HOST_CONTROL2, ctrl_2); +/* device_printf(brdev,"SUPER FAKE timing\n"); */ +} +static void +sdhci_fdt_set_uhs_timing(device_t brdev, struct sdhci_slot *slot) +{ +if (ofw_bus_search_compatible(brdev, compat_data)->ocd_data == + SDHCI_FDT_RK3568) { + rk35xx_set_uhs_timing(brdev, slot); + return; + } else { + device_printf(brdev, "UHS timings not implemented -- card might not work in UHS mode\n"); + } +} + static int sdhci_fdt_set_clock(device_t dev, struct sdhci_slot *slot, int clock) { struct sdhci_fdt_softc *sc = device_get_softc(dev); int32_t val; + uint32_t uval; int i; if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == SDHCI_FDT_RK3568) { if (clock == 400000) clock = 375000; - if (clock) { clk_set_freq(sc->clk_core, clock, 0); + uval = bus_read_4(sc->mem_res[slot->num], RK3568_EMMC_HOST_CTRL) & (~1); + bus_write_4(sc->mem_res[slot->num], RK3568_EMMC_HOST_CTRL, uval); if (clock <= 52000000) { bus_write_4(sc->mem_res[slot->num], - RK3568_EMMC_DLL_CTRL, 0x0); + RK3568_EMMC_DLL_CTRL, DLL_CTRL_START|DLL_CTRL_BYPASS); bus_write_4(sc->mem_res[slot->num], RK3568_EMMC_DLL_RXCLK, DLL_RXCLK_NO_INV); bus_write_4(sc->mem_res[slot->num], RK3568_EMMC_DLL_TXCLK, 0x0); bus_write_4(sc->mem_res[slot->num], - RK3568_EMMC_DLL_STRBIN, 0x0); + RK3568_EMMC_DLL_CMDOUT, 0x0); + + uval = DLL_STRBIN_DELAY_ENABLE | DLL_STRBIN_DELAY_NUM_SEL | + DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET; + bus_write_4(sc->mem_res[slot->num], RK3568_EMMC_DLL_STRBIN, uval); return (clock); } @@ -481,13 +579,13 @@ sdhci_fdt_set_clock(device_t dev, struct sdhci_slot *slot, int clock) DELAY(1000); } bus_write_4(sc->mem_res[slot->num], RK3568_EMMC_ATCTRL, - (0x1 << 16 | 0x2 << 17 | 0x3 << 19)); + (0x1 << 16 | 0x3 << 17 | 0x3 << 19)); bus_write_4(sc->mem_res[slot->num], RK3568_EMMC_DLL_RXCLK, DLL_RXCLK_DELAY_ENABLE | DLL_RXCLK_NO_INV); bus_write_4(sc->mem_res[slot->num], RK3568_EMMC_DLL_TXCLK, DLL_TXCLK_DELAY_ENABLE | - DLL_TXCLK_TAPNUM_DEFAULT|DLL_TXCLK_TAPNUM_FROM_SW); + DLL_TXCLK_TAPNUM_DEFAULT|DLL_TXCLK_TAPNUM_FROM_SW | DLL_RXCLK_NO_INV); bus_write_4(sc->mem_res[slot->num], RK3568_EMMC_DLL_STRBIN, DLL_STRBIN_DELAY_ENABLE | DLL_STRBIN_TAPNUM_DEFAULT | @@ -516,9 +614,6 @@ sdhci_fdt_probe(device_t dev) sc->quirks = SDHCI_QUIRK_BROKEN_AUTO_STOP; device_set_desc(dev, "ARMADA38X SDHCI controller"); break; - case SDHCI_FDT_GENERIC: - device_set_desc(dev, "generic fdt SDHCI controller"); - break; case SDHCI_FDT_QUALCOMM: sc->quirks = SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | SDHCI_QUIRK_BROKEN_SDMA_BOUNDARY; @@ -533,6 +628,7 @@ sdhci_fdt_probe(device_t dev) device_set_desc(dev, "Zynq-7000 generic fdt SDHCI controller"); break; case SDHCI_FDT_RK3568: + sc->quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; device_set_desc(dev, "Rockchip RK3568 fdt SDHCI controller"); break; case SDHCI_FDT_XLNX_ZMP: @@ -566,7 +662,8 @@ sdhci_fdt_attach(device_t dev) { struct sdhci_fdt_softc *sc = device_get_softc(dev); struct sdhci_slot *slot; - int err, slots, rid, i; + int err, slots, rid, i, compat; + uint32_t temp; sc->dev = dev; @@ -579,24 +676,41 @@ sdhci_fdt_attach(device_t dev) return (ENOMEM); } - if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == - SDHCI_FDT_RK3399) { - /* Initialize SDHCI */ - err = sdhci_init_rk3399(dev); + compat = ofw_bus_search_compatible(dev, compat_data)->ocd_data; + switch (compat) { + case SDHCI_FDT_RK3399: + case SDHCI_FDT_XLNX_ZMP: + err = sdhci_init_clocks(dev); if (err != 0) { - device_printf(dev, "Cannot init RK3399 SDHCI\n"); + device_printf(dev, "Cannot init clocks\n"); return (err); } - } - - if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == - SDHCI_FDT_RK3568) { - /* setup & enable clocks */ - if (clk_get_by_ofw_name(dev, 0, "core", &sc->clk_core)) { - device_printf(dev, "cannot get core clock\n"); - return (ENXIO); + sdhci_export_clocks(sc); + if ((err = sdhci_init_phy(sc)) != 0) { + device_printf(dev, "Cannot init phy\n"); + return (err); + } + if ((err = sdhci_get_syscon(sc)) != 0) { + device_printf(dev, "Cannot get syscon handle\n"); + return (err); } - clk_enable(sc->clk_core); + if (compat == SDHCI_FDT_RK3399) { + err = sdhci_init_rk3399(dev); + if (err != 0) { + device_printf(dev, "Cannot init RK3399 SDHCI\n"); + return (err); + } + } + break; + case SDHCI_FDT_RK3568: + err = sdhci_init_rk3568(dev); + if (err != 0) { + device_printf(dev, "Cannot init RK3568 SDHCI\n"); + return (err); + } + break; + default: + break; } /* Scan all slots. */ @@ -619,7 +733,12 @@ sdhci_fdt_attach(device_t dev) slot->caps = sc->caps; slot->max_clk = sc->max_clk; slot->sdma_boundary = sc->sdma_boundary; - + if(compat == SDHCI_FDT_RK3568) { + temp = sdhci_fdt_read_4(dev, slot, RK3568_EMMC_HOST_CTRL) & (~1); + sdhci_fdt_write_4(dev, slot, RK3568_EMMC_HOST_CTRL, temp); + } + sdhci_fdt_write_4(dev, slot, RK3568_EMMC_DLL_TXCLK, 0); + sdhci_fdt_write_4(dev, slot, RK3568_EMMC_DLL_STRBIN, 0); if (sdhci_init_slot(dev, slot, i) != 0) continue; @@ -678,6 +797,10 @@ static device_method_t sdhci_fdt_methods[] = { DEVMETHOD(mmcbr_get_ro, sdhci_fdt_get_ro), DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), + DEVMETHOD(mmcbr_tune, sdhci_generic_tune), + DEVMETHOD(mmcbr_retune, sdhci_generic_retune), + DEVMETHOD(mmcbr_switch_vccq, sdhci_generic_switch_vccq), + /* SDHCI registers accessors */ DEVMETHOD(sdhci_read_1, sdhci_fdt_read_1), @@ -689,7 +812,7 @@ static device_method_t sdhci_fdt_methods[] = { DEVMETHOD(sdhci_write_4, sdhci_fdt_write_4), DEVMETHOD(sdhci_write_multi_4, sdhci_fdt_write_multi_4), DEVMETHOD(sdhci_set_clock, sdhci_fdt_set_clock), - + DEVMETHOD(sdhci_set_uhs_timing, sdhci_fdt_set_uhs_timing), DEVMETHOD_END }; diff --git a/sys/dev/uart/uart_dev_ns8250.c b/sys/dev/uart/uart_dev_ns8250.c index de9b67c6bef1..e90085e80e87 100644 --- a/sys/dev/uart/uart_dev_ns8250.c +++ b/sys/dev/uart/uart_dev_ns8250.c @@ -55,7 +55,7 @@ #include #ifdef DEV_ACPI #include -#include +/* #include */ #endif #include @@ -444,9 +444,9 @@ struct uart_class uart_ns8250_class = { */ #ifdef DEV_ACPI static struct acpi_uart_compat_data acpi_compat_data[] = { - {"AMD0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, + {"AMD0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, {"AMDI0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, - {"MRVL0001", &uart_ns8250_class, ACPI_DBG2_16550_SUBSET, 2, 0, 200000000, UART_F_BUSY_DETECT, "Marvell / Synopsys Designware UART"}, + {"MRVL0001", &uart_ns8250_class, 0, 2, 0, 200000000, UART_F_BUSY_DETECT, "Marvell / Synopsys Designware UART"}, {"SCX0006", &uart_ns8250_class, 0, 2, 0, 62500000, UART_F_BUSY_DETECT, "SynQuacer / Synopsys Designware UART"}, {"HISI0031", &uart_ns8250_class, 0, 2, 0, 200000000, UART_F_BUSY_DETECT, "HiSilicon / Synopsys Designware UART"}, {"NXP0018", &uart_ns8250_class, 0, 0, 0, 350000000, UART_F_BUSY_DETECT, "NXP / Synopsys Designware UART"}, diff --git a/sys/modules/dtb/rockchip/Makefile b/sys/modules/dtb/rockchip/Makefile index 79ce7f2c7407..aa8fba69bd6f 100644 --- a/sys/modules/dtb/rockchip/Makefile +++ b/sys/modules/dtb/rockchip/Makefile @@ -6,17 +6,24 @@ DTS= \ rk3288-tinker-s.dts .elif ${MACHINE_ARCH} == "aarch64" DTS= \ - rockchip/rk3399-khadas-edge-captain.dts \ rockchip/rk3399-khadas-edge.dts \ rockchip/rk3399-khadas-edge-v.dts \ rockchip/rk3399-nanopc-t4.dts \ rockchip/rk3328-nanopi-r2s.dts \ rockchip/rk3399-nanopi-r4s.dts \ + rockchip/rk3399-nanopi-r4se.dts \ rockchip/rk3399-rock-pi-4.dts \ rockchip/rk3328-rock-pi-e.dts \ rockchip/rk3328-rock64.dts \ rockchip/rk3399-firefly.dts \ - rockchip/rk3399-rockpro64.dts + rockchip/rk3399-rockpro64.dts \ + rockchip/rk3399pro-rock-pi-n10.dts \ + rockchip/rk3566-roc-pc.dts \ + rockchip/rk3568-nanopi-r5c.dts \ + rockchip/rk3568-nanopi-r5s.dts \ + rockchip/rk3568-radxa-e25.dts \ + rockchip/rk3568-roc-pc.dts \ + rockchip/rk3568-rock-3a.dts DTSO= rk3328-analog-sound.dtso \ rk3328-i2c0.dtso \ diff --git a/usr.sbin/bsdinstall/scripts/auto b/usr.sbin/bsdinstall/scripts/auto index fd5b634696ae..35aed437fedd 100755 --- a/usr.sbin/bsdinstall/scripts/auto +++ b/usr.sbin/bsdinstall/scripts/auto @@ -49,6 +49,7 @@ msg_auto_zfs_desc="Guided Root-on-ZFS" msg_auto_zfs_help="To use ZFS with less than 8GB RAM, see https://wiki.freebsd.org/ZFSTuningGuide" msg_exit="Exit" msg_freebsd_installer="$OSNAME Installer" +msg_gpt_rockchip_fix="Your Rockchip SoC is known to have a feature that needs to be taken into account when installing the system on an eMMC. Do you want the installer to apply a workaround for you?" msg_gpt_active_fix="Your hardware is known to have issues booting in CSM/Legacy/BIOS mode from GPT partitions that are not set active. Would you like the installer to apply this workaround for you?" msg_lenovo_fix="Your model of Lenovo is known to have a BIOS bug that prevents it booting from GPT partitions without UEFI. Would you like the installer to apply a workaround for you?" msg_manual="Manual" @@ -145,7 +146,7 @@ f_dprintf "Began Installation at %s" "$( date )" rm -rf $BSDINSTALL_TMPETC mkdir $BSDINSTALL_TMPETC -[ -f /usr/libexec/bsdinstall/local.pre-everything ] && f_dprintf "Running local.pre-everything" && sh /usr/libexec/bsdinstall/local.pre-everything "$BSDINSTALL_CHROOT" +[ -f /usr/libexec/bsdinstall/local.pre-everything ] && f_dprintf "Running local.pre-everything" && . /usr/libexec/bsdinstall/local.pre-everything "$BSDINSTALL_CHROOT" trap true SIGINT # This section is optional [ -z "$BSDINSTALL_SKIP_KEYMAP" ] && bsdinstall keymap @@ -188,16 +189,16 @@ fi rm -f $PATH_FSTAB touch $PATH_FSTAB -[ -f /usr/libexec/bsdinstall/local.pre-partition ] && f_dprintf "Running local.pre-partition" && sh /usr/libexec/bsdinstall/local.pre-partition "$BSDINSTALL_CHROOT" +[ -f /usr/libexec/bsdinstall/local.pre-partition ] && f_dprintf "Running local.pre-partition" && . /usr/libexec/bsdinstall/local.pre-partition "$BSDINSTALL_CHROOT" # # Try to detect known broken platforms and apply their workarounds # if f_interactive; then - sys_maker=$( kenv -q smbios.system.maker ) + sys_maker=$( kenv -q smbios.system.maker | tr 'A-Z' 'a-z' | tr ' ' '-' ) f_dprintf "smbios.system.maker=[%s]" "$sys_maker" - sys_model=$( kenv -q smbios.system.product ) + sys_model=$( kenv -q smbios.system.product | tr 'A-Z' 'a-z' | tr ' ' '-' ) f_dprintf "smbios.system.product=[%s]" "$sys_model" sys_version=$( kenv -q smbios.system.version ) f_dprintf "smbios.system.version=[%s]" "$sys_version" @@ -206,11 +207,33 @@ if f_interactive; then sys_mb_product=$( kenv -q smbios.planar.product ) f_dprintf "smbios.planar.product=[%s]" "$sys_mb_product" + # + # Boards based on Rockchip SoC + # + case "$sys_maker" in + # serg + "firefly"|"friendlyelec"|"friendlyarm"|"kobol"|"orangepi"|"orange-pi"|"radxa"|"pine64") + # TODO + dialog_workaround "$msg_gpt_rockchip_fix" + retval=$? + f_dprintf "gpt_rockchip_fix_prompt=[%s]" "$retval" + if [ $retval -eq $DIALOG_OK ]; then + export ZFSBOOT_PARTITION_SCHEME="GPT" + export WORKAROUND_ROCKCHIP=1 + #smbios.bios.vendor="U-Boot" + export BOOTLOADER=$( kenv -q smbios.bios.vendor | tr 'A-Z' 'a-z' ) + #smbios.system.product="NanoPi-R4S" + export PRODUCT=$( kenv -q smbios.system.product | tr 'A-Z' 'a-z' | tr ' ' '-' ) + fi + ;; + esac + # serg + # # Laptop Models # case "$sys_maker" in - "LENOVO") + "lenovo") case "$sys_version" in "ThinkPad X220"|"ThinkPad T420"|"ThinkPad T520"|"ThinkPad W520"|"ThinkPad X1") dialog_workaround "$msg_lenovo_fix" @@ -223,7 +246,7 @@ if f_interactive; then ;; esac ;; - "Dell Inc.") + "dell-inc.") case "$sys_model" in "Latitude E6330"|"Latitude E7440"|"Latitude E7240"|"Precision Tower 5810") dialog_workaround "$msg_gpt_active_fix" @@ -236,7 +259,7 @@ if f_interactive; then ;; esac ;; - "Hewlett-Packard") + "hewlett-packard") case "$sys_model" in "HP ProBook 4330s") dialog_workaround "$msg_gpt_active_fix" @@ -254,7 +277,7 @@ if f_interactive; then # Motherboard Models # case "$sys_mb_maker" in - "Intel Corporation") + "intel-corporation") case "$sys_mb_product" in "DP965LT"|"D510MO") dialog_workaround "$msg_gpt_active_fix" @@ -267,7 +290,7 @@ if f_interactive; then ;; esac ;; - "Acer") + "acer") case "$sys_mb_product" in "Veriton M6630G") dialog_workaround "$msg_gpt_active_fix" @@ -283,11 +306,18 @@ if f_interactive; then esac fi +# serg +if [ $WORKAROUND_ROCKCHIP ]; then +PMODES=" + '$msg_shell' '$msg_shell_desc' '$msg_shell_help' +" # END-QUOTE +else PMODES=" '$msg_auto_ufs' '$msg_auto_ufs_desc' '$msg_auto_ufs_help' '$msg_manual' '$msg_manual_desc' '$msg_manual_help' '$msg_shell' '$msg_shell_desc' '$msg_shell_help' " # END-QUOTE +fi CURARCH=$( uname -m ) case $CURARCH in @@ -337,7 +367,7 @@ case "$PARTMODE" in ;; esac -[ -f /usr/libexec/bsdinstall/local.pre-fetch ] && f_dprintf "Running local.pre-fetch" && sh /usr/libexec/bsdinstall/local.pre-fetch "$BSDINSTALL_CHROOT" +[ -f /usr/libexec/bsdinstall/local.pre-fetch ] && f_dprintf "Running local.pre-fetch" && . /usr/libexec/bsdinstall/local.pre-fetch "$BSDINSTALL_CHROOT" if [ -n "$FETCH_DISTRIBUTIONS" ]; then exec 3>&1 @@ -353,7 +383,7 @@ bsdinstall distextract || error "Distribution extract failed" # Set up boot loader bsdinstall bootconfig || error "Failed to configure bootloader" -[ -f /usr/libexec/bsdinstall/local.pre-configure ] && f_dprintf "Running local.pre-configure" && sh /usr/libexec/bsdinstall/local.pre-configure "$BSDINSTALL_CHROOT" +[ -f /usr/libexec/bsdinstall/local.pre-configure ] && f_dprintf "Running local.pre-configure" && . /usr/libexec/bsdinstall/local.pre-configure "$BSDINSTALL_CHROOT" bsdinstall rootpass || error "Could not set root password" @@ -432,7 +462,7 @@ if [ ! -z "$BSDINSTALL_FETCHDEST" ]; then rm -rf "$BSDINSTALL_FETCHDEST" fi -[ -f /usr/libexec/bsdinstall/local.post-configure ] && f_dprintf "Running local.post-configure" && sh /usr/libexec/bsdinstall/local.post-configure "$BSDINSTALL_CHROOT" +[ -f /usr/libexec/bsdinstall/local.post-configure ] && f_dprintf "Running local.post-configure" && . /usr/libexec/bsdinstall/local.post-configure "$BSDINSTALL_CHROOT" if [ -z "$BSDINSTALL_SKIP_MANUAL" ]; then dialog --backtitle "$OSNAME Installer" --title "Manual Configuration" \ diff --git a/usr.sbin/bsdinstall/scripts/bootconfig b/usr.sbin/bsdinstall/scripts/bootconfig index bd69195f76ff..fadd8552b000 100755 --- a/usr.sbin/bsdinstall/scripts/bootconfig +++ b/usr.sbin/bsdinstall/scripts/bootconfig @@ -99,6 +99,48 @@ if [ `uname -m` == powerpc ]; then fi fi +if [ `uname -m` == "arm64" ]; then + if [ -e /dev/mmcsd1 ]; then + DISK_MD=mmcsd1 + f_dprintf "Drive /dev/${DISK_MD} selected for EFI installation" + else + if [ -e /dev/mmcsd0 ]; then + DISK_MD=mmcsd0 + f_dprintf "Drive /dev/${DISK_MD} selected for EFI installation" + fi + fi + f_dprintf "BOOTCONFIG U-Boot for ${PRODUCT} to /dev/${DISK_MD}" + if [ ! -z ${PRODUCT} ]; then + if [ -d /usr/local/share/u-boot/u-boot-${PRODUCT} ]; then + UBOOT_PATH="/usr/local/share/u-boot/u-boot-${PRODUCT}" + f_dprintf "Installing ${UBOOT_PATH} to /dev/${DISK_MD}" + fi + fi + # Mainline U-Boot for FreeBSD + if [ -e /dev/${DISK_MD} ]; then + sysctl kern.geom.debugflags=0x10 2>&1 + if [ -f ${UBOOT_PATH}/u-boot.itb ]; then + dd if=${UBOOT_PATH}/idbloader.img of=/dev/${DISK_MD} conv=sync bs=512 seek=64 + dd if=${UBOOT_PATH}/u-boot.itb of=/dev/${DISK_MD} conv=sync bs=512 seek=16384 + fi + if [ -f ${UBOOT_PATH}/trust.img ]; then + dd if=${UBOOT_PATH}/idbloader.img of=/dev/${DISK_MD} conv=sync bs=512 seek=64 + dd if=${UBOOT_PATH}/uboot.img of=/dev/${DISK_MD} conv=sync bs=512 seek=16384 + dd if=${UBOOT_PATH}/trust.img of=/dev/${DISK_MD} conv=sync bs=512 seek=24576 + fi + if [ -f ${UBOOT_PATH}/u-boot-sunxi-with-spl.bin ]; then + dd if=${UBOOT_PATH}/u-boot-sunxi-with-spl.bin of=/dev/${DISK_MD} bs=1k seek=8 conv=sync + fi + fi + mkdir -p $BSDINSTALL_CHROOT/boot/efi + if [ -f ${UBOOT_PATH}/splash.bmp ]; then + cp ${UBOOT_PATH}/splash.bmp $BSDINSTALL_CHROOT/boot/efi + fi + if [ -f ${UBOOT_PATH}/u-boot-spi.bin ]; then + cp ${UBOOT_PATH}/u-boot-spi.bin $BSDINSTALL_CHROOT/boot/efi + fi +fi + # Update the ESP (EFI System Partition) with the new bootloader if we have an ESP if [ -n "$(awk '{if ($2=="/boot/efi") printf("%s\n",$1);}' $PATH_FSTAB)" ]; then case $(uname -m) in diff --git a/usr.sbin/bsdinstall/scripts/config b/usr.sbin/bsdinstall/scripts/config index 093d38ee0a59..b506a852b2ad 100755 --- a/usr.sbin/bsdinstall/scripts/config +++ b/usr.sbin/bsdinstall/scripts/config @@ -31,6 +31,9 @@ cat $BSDINSTALL_TMPETC/rc.conf.* >> $BSDINSTALL_TMPETC/rc.conf rm $BSDINSTALL_TMPETC/rc.conf.* +# Small tuning +tail +10 /etc/sysctl.conf >> $BSDINSTALL_TMPETC/sysctl.conf.local + cat $BSDINSTALL_CHROOT/etc/sysctl.conf $BSDINSTALL_TMPETC/sysctl.conf.* >> $BSDINSTALL_TMPETC/sysctl.conf rm $BSDINSTALL_TMPETC/sysctl.conf.* @@ -41,15 +44,57 @@ fi cp $BSDINSTALL_TMPETC/* $BSDINSTALL_CHROOT/etc -cat $BSDINSTALL_TMPBOOT/loader.conf.* >> $BSDINSTALL_TMPBOOT/loader.conf -rm $BSDINSTALL_TMPBOOT/loader.conf.* +if [ "$WORKAROUND_ROCKCHIP" ]; then + echo '# Hack loader for RockChip' >> $BSDINSTALL_TMPBOOT/loader.conf + echo 'hw.regulator.disable_unused="0"' >> $BSDINSTALL_TMPBOOT/loader.conf + echo '' >> $BSDINSTALL_TMPBOOT/loader.conf + echo '# Maximize CPU fequency' >> $BSDINSTALL_TMPBOOT/loader.conf + echo '#dev.cpu.0.freq="1008"' >> $BSDINSTALL_TMPBOOT/loader.conf + echo '' >> $BSDINSTALL_TMPBOOT/loader.conf + echo '# Multiple console enabled.' >> $BSDINSTALL_TMPBOOT/loader.conf + echo '#boot_serial="YES"' >> $BSDINSTALL_TMPBOOT/loader.conf + echo '#boot_multicons="YES"' >> $BSDINSTALL_TMPBOOT/loader.conf + echo '' >> $BSDINSTALL_TMPBOOT/loader.conf + echo '# EFI console enabled.' >> $BSDINSTALL_TMPBOOT/loader.conf + echo '#console="efi"' >> $BSDINSTALL_TMPBOOT/loader.conf + echo '' >> $BSDINSTALL_TMPBOOT/loader.conf +fi + +# Install precompiled realtek-re-kmod for RTL8125 +ifconfig -l | grep -q re0 && export WORKAROUND_REALTEK=1 +if [ "$WORKAROUND_REALTEK" ]; then + cp -r /boot/modules $BSDINSTALL_CHROOT/boot + echo '# RealTek RTL8125' >> $BSDINSTALL_TMPBOOT/loader.conf + echo 'if_re_load="YES"' >> $BSDINSTALL_TMPBOOT/loader.conf + echo 'if_re_name="/boot/modules/if_re.ko"' >> $BSDINSTALL_TMPBOOT/loader.conf + echo 'hw.re.max_rx_mbuf_sz="2048"' >> $BSDINSTALL_TMPBOOT/loader.conf + echo '' >> $BSDINSTALL_TMPBOOT/loader.conf +fi + # The 'cryptodev_load' line is a workaround for arm64, which does not # automatically load cryptodev.ko with zfs.ko. +df -t zfs $BSDINSTALL_CHROOT > /dev/null && echo '# ZFS Settings' >> $BSDINSTALL_TMPBOOT/loader.conf df -t zfs $BSDINSTALL_CHROOT > /dev/null && echo "cryptodev_load=\"YES\"" >> $BSDINSTALL_TMPBOOT/loader.conf -df -t zfs $BSDINSTALL_CHROOT > /dev/null && echo "zfs_load=\"YES\"" >> $BSDINSTALL_TMPBOOT/loader.conf +df -t zfs $BSDINSTALL_CHROOT > /dev/null && echo "zfs_load=\"YES\"" >> $BSDINSTALL_TMPBOOT/loader.conf +df -t zfs $BSDINSTALL_CHROOT > /dev/null && echo '' >> $BSDINSTALL_TMPBOOT/loader.conf + +cat $BSDINSTALL_TMPBOOT/loader.conf.* >> $BSDINSTALL_TMPBOOT/loader.conf +rm $BSDINSTALL_TMPBOOT/loader.conf.* cp $BSDINSTALL_TMPBOOT/* $BSDINSTALL_CHROOT/boot +# Custom Repo and local distribution +if [ -d /usr/local/etc/pkg/repos ]; then + mkdir -p $BSDINSTALL_CHROOT/usr/local/etc + cp -r /usr/local/etc/pkg $BSDINSTALL_CHROOT/root + #cp -r /usr/local/etc/pkg $BSDINSTALL_CHROOT/usr/local/etc +fi + +# Enable custom loader settings +if [ -d /boot/loader.conf.d ]; then + cp -r /boot/loader.conf.d $BSDINSTALL_CHROOT/boot +fi + [ "${debugFile#+}" ] && cp "${debugFile#+}" $BSDINSTALL_CHROOT/var/log/ # Set up other things from installed config diff --git a/usr.sbin/bsdinstall/scripts/zfsboot b/usr.sbin/bsdinstall/scripts/zfsboot index a671841b15e5..0f43de08d68c 100755 --- a/usr.sbin/bsdinstall/scripts/zfsboot +++ b/usr.sbin/bsdinstall/scripts/zfsboot @@ -833,8 +833,15 @@ zfs_create_diskpart() if [ "$ZFSBOOT_FORCE_4K_SECTORS" ]; then align_small="-a 4k" align_big="-a 1m" + efi_size="260m" fi + if [ "$WORKAROUND_ROCKCHIP" ]; then + align_small="-b 16m -a 512k" + align_big="-a 64k" + efi_size="50m" + fi + case "$ZFSBOOT_PARTITION_SCHEME" in ""|GPT*) f_dprintf "$funcname: Creating GPT layout..." # @@ -862,21 +869,22 @@ zfs_create_diskpart() then f_eval_catch -k justaddedpart $funcname gpart \ "$GPART_ADD_ALIGN_LABEL_WITH_SIZE" \ - "$align_small" efiboot$index efi 260M \ + "$align_small" efi$index efi $efi_size \ $disk || return $FAILURE # We'll configure the ESP in bootconfig if [ -z "$efibootpart" ]; then - efibootpart="/dev/gpt/efiboot$index" + efibootpart="/dev/gpt/efi$index" f_dprintf "$funcname: configuring ESP at [%s]" \ "${efibootpart}" f_eval_catch $funcname newfs_msdos "$NEWFS_ESP"\ "$efibootpart" \ || return $FAILURE + # serg isuse f_eval_catch $funcname printf "$PRINTF_FSTAB" \ $efibootpart /boot/efi msdosfs \ - rw 2 2 "$BSDINSTALL_TMPETC/fstab" \ + rw,noauto 0 0 "$BSDINSTALL_TMPETC/fstab" \ || return $FAILURE fi fi @@ -956,14 +964,14 @@ zfs_create_diskpart() # # 4. Add freebsd-zfs partition labeled `zfs#' for zroot - # + # change zfz to root if [ "$ZFSBOOT_POOL_SIZE" ]; then f_eval_catch $funcname gpart "$GPART_ADD_ALIGN_LABEL_WITH_SIZE" \ - "$align_big" zfs$index freebsd-zfs $ZFSBOOT_POOL_SIZE $disk || + "$align_big" root$index freebsd-zfs $ZFSBOOT_POOL_SIZE $disk || return $FAILURE else f_eval_catch $funcname gpart "$GPART_ADD_ALIGN_LABEL" \ - "$align_big" zfs$index freebsd-zfs $disk || + "$align_big" root$index freebsd-zfs $disk || return $FAILURE fi f_eval_catch -d $funcname zpool "$ZPOOL_LABELCLEAR_F" \ @@ -1077,9 +1085,10 @@ zfs_create_diskpart() f_eval_catch $funcname printf "$PRINTF_FSTAB" \ /dev/$disk${swappart}.eli none swap sw 0 0 \ $BSDINSTALL_TMPETC/fstab || return $FAILURE - else + else # serg +# /dev/$disk$swappart none swap sw 0 0 f_eval_catch $funcname printf "$PRINTF_FSTAB" \ - /dev/$disk$swappart none swap sw 0 0 \ + /dev/gpt/swap$index none swap sw 0 0 \ $BSDINSTALL_TMPETC/fstab || return $FAILURE fi @@ -1187,7 +1196,7 @@ zfs_create_boot() f_dprintf "$funcname: With 4K sectors..." f_eval_catch $funcname sysctl "$SYSCTL_ZFS_MIN_ASHIFT_12" \ || return $FAILURE - sysctl kern.geom.part.mbr.enforce_chs=0 + sysctl kern.geom.part.mbr.enforce_chs=0 2>&1 fi local n=0 for disk in $disks; do