--- arch/arm/dts/rk3328.dtsi.orig 2020-07-06 22:22:53.000000000 +0300 +++ arch/arm/dts/rk3328.dtsi 2021-07-11 22:42:30.475388000 +0300 @@ -233,7 +233,8 @@ clock-names = "i2s_clk", "i2s_hclk"; dmas = <&dmac 11>, <&dmac 12>; dma-names = "tx", "rx"; - #sound-dai-cells = <0>; + resets = <&cru SRST_I2S0>, <&cru SRST_I2S0_H>; + reset-names = "reset-m", "reset-h"; status = "disabled"; }; @@ -245,7 +246,8 @@ clock-names = "i2s_clk", "i2s_hclk"; dmas = <&dmac 14>, <&dmac 15>; dma-names = "tx", "rx"; - #sound-dai-cells = <0>; + resets = <&cru SRST_I2S1>, <&cru SRST_I2S1_H>; + reset-names = "reset-m", "reset-h"; status = "disabled"; }; @@ -257,7 +259,16 @@ clock-names = "i2s_clk", "i2s_hclk"; dmas = <&dmac 0>, <&dmac 1>; dma-names = "tx", "rx"; - #sound-dai-cells = <0>; + resets = <&cru SRST_I2S2>, <&cru SRST_I2S2_H>; + reset-names = "reset-m", "reset-h"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2s2m0_mclk + &i2s2m0_sclk + &i2s2m0_lrcktx + &i2s2m0_lrckrx + &i2s2m0_sdo + &i2s2m0_sdi>; + pinctrl-1 = <&i2s2m0_sleep>; status = "disabled"; }; @@ -271,7 +282,6 @@ dma-names = "tx"; pinctrl-names = "default"; pinctrl-0 = <&spdifm2_tx>; - #sound-dai-cells = <0>; status = "disabled"; }; @@ -295,7 +305,42 @@ &pdmm0_sdi3_sleep>; status = "disabled"; }; + + tsp: tsp@ff050000 { + compatible = "rockchip,rk3328-tsp"; + reg = <0x0 0xff050000 0x0 0x10000>; + rockchip,grf = <&grf>; + interrupts = ; + interrupt-names = "irq_tsp"; + clocks = <&cru SCLK_TSP>, <&cru ACLK_TSP>, <&cru HCLK_TSP>; + clock-names = "clk_tsp", "aclk_tsp", "hclk_tsp"; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_d0 + &tsp_d1 + &tsp_d2 + &tsp_d3 + &tsp_d4 + &tsp_d5 + &tsp_d6 + &tsp_d7 + &tsp_sync + &tsp_clk + &tsp_fail + &tsp_valid>; + status = "disabled"; + }; + rng: rng@ff060000 { + compatible = "rockchip,cryptov1-rng"; + reg = <0x0 0xff060000 0x0 0x4000>; + + clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>; + clock-names = "clk_crypto", "hclk_crypto"; + assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>; + assigned-clock-rates = <150000000>, <100000000>; + status = "disabled"; + }; + grf: syscon@ff100000 { compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; reg = <0x0 0xff100000 0x0 0x1000>; @@ -322,6 +367,10 @@ }; pd_video@RK3328_PD_VIDEO { reg = ; + clocks = <&cru ACLK_RKVDEC>, + <&cru HCLK_RKVDEC>, + <&cru SCLK_VDEC_CABAC>, + <&cru SCLK_VDEC_CORE>; }; pd_vpu@RK3328_PD_VPU { reg = ; @@ -384,6 +433,11 @@ status = "disabled"; }; + pmu: power-management@ff140000 { + compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xff140000 0x0 0x1000>; + }; + i2c0: i2c@ff150000 { compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0xff150000 0x0 0x1000>; @@ -602,7 +656,7 @@ gpu: gpu@ff300000 { compatible = "rockchip,rk3328-mali", "arm,mali-450"; - reg = <0x0 0xff300000 0x0 0x40000>; + reg = <0x0 0xff300000 0x0 0x30000>; interrupts = , , , @@ -674,6 +728,7 @@ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; clock-names = "aclk", "iface"; #iommu-cells = <0>; + power-domains = <&power RK3328_PD_VIDEO>; status = "disabled"; }; @@ -833,6 +888,13 @@ assigned-clock-parents = <&u2phy>; status = "disabled"; + u2phy_host: host-port { + #phy-cells = <0>; + interrupts = ; + interrupt-names = "linestate"; + status = "disabled"; + }; + u2phy_otg: otg-port { #phy-cells = <0>; interrupts = , @@ -842,16 +904,50 @@ "linestate"; status = "disabled"; }; - - u2phy_host: host-port { - #phy-cells = <0>; - interrupts = ; - interrupt-names = "linestate"; - status = "disabled"; - }; }; }; + usb3phy_grf: syscon@ff460000 { + compatible = "rockchip,usb3phy-grf", "syscon"; + reg = <0x0 0xff460000 0x0 0x1000>; + }; + + u3phy: usb3-phy@ff470000 { + compatible = "rockchip,rk3328-u3phy"; + reg = <0x0 0xff470000 0x0 0x0>; + rockchip,u3phygrf = <&usb3phy_grf>; + rockchip,grf = <&grf>; + interrupts = ; + interrupt-names = "linestate"; + clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>; + clock-names = "u3phy-otg", "u3phy-pipe"; + resets = <&cru SRST_USB3PHY_U2>, + <&cru SRST_USB3PHY_U3>, + <&cru SRST_USB3PHY_PIPE>, + <&cru SRST_USB3OTG_UTMI>, + <&cru SRST_USB3PHY_OTG_P>, + <&cru SRST_USB3PHY_PIPE_P>; + reset-names = "u3phy-u2-por", "u3phy-u3-por", + "u3phy-pipe-mac", "u3phy-utmi-mac", + "u3phy-utmi-apb", "u3phy-pipe-apb"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + u3phy_utmi: utmi@ff470000 { + reg = <0x0 0xff470000 0x0 0x8000>; + #phy-cells = <0>; + status = "disabled"; + }; + + u3phy_pipe: pipe@ff478000 { + reg = <0x0 0xff478000 0x0 0x8000>; + #phy-cells = <0>; + status = "disabled"; + }; + }; + sdmmc: mmc@ff500000 { compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff500000 0x0 0x4000>; @@ -861,6 +957,8 @@ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; max-frequency = <150000000>; + resets = <&cru SRST_MMC0>; + reset-names = "reset"; status = "disabled"; }; @@ -873,6 +971,8 @@ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; max-frequency = <150000000>; + resets = <&cru SRST_SDIO>; + reset-names = "reset"; status = "disabled"; }; @@ -885,12 +985,15 @@ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; max-frequency = <150000000>; + resets = <&cru SRST_EMMC>; + reset-names = "reset"; status = "disabled"; }; gmac2io: ethernet@ff540000 { compatible = "rockchip,rk3328-gmac"; reg = <0x0 0xff540000 0x0 0x10000>; + rockchip,grf = <&grf>; interrupts = ; interrupt-names = "macirq"; clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, @@ -903,7 +1006,6 @@ "pclk_mac"; resets = <&cru SRST_GMAC2IO_A>; reset-names = "stmmaceth"; - rockchip,grf = <&grf>; snps,txpbl = <0x4>; status = "disabled"; }; @@ -946,51 +1048,92 @@ }; }; - usb_host0_ehci: usb@ff5c0000 { - compatible = "generic-ehci"; - reg = <0x0 0xff5c0000 0x0 0x10000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>, <&u2phy>; - phys = <&u2phy_host>; - phy-names = "usb"; + sdmmc_ext: dwmmc@ff5f0000 { + compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff5f0000 0x0 0x4000>; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>, + <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; status = "disabled"; - }; + }; - usb_host0_ohci: usb@ff5d0000 { - compatible = "generic-ohci"; - reg = <0x0 0xff5d0000 0x0 0x10000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>, <&u2phy>; - phys = <&u2phy_host>; - phy-names = "usb"; + usbdrd3: usb@ff600000 { + compatible = "rockchip,rk3328-dwc3"; + clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>, + <&cru ACLK_USB3OTG>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk"; + resets = <&cru SRST_USB3OTG>; + reset-names = "usb3-otg"; + #address-cells = <2>; + #size-cells = <2>; + ranges; status = "disabled"; + + usbdrd_dwc3: dwc3@ff600000 { + compatible = "snps,dwc3"; + reg = <0x0 0xff600000 0x0 0x100000>; + interrupts = ; + clocks = <&cru SCLK_USB3OTG_REF>, <&cru ACLK_USB3OTG>, + <&cru SCLK_USB3OTG_SUSPEND>; + clock-names = "ref", "bus_early", "suspend"; + dr_mode = "host"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,dis-u3-autosuspend-quirk; + snps,dis_u3_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,tx-ipgap-linecheck-dis-quirk; + status = "disabled"; + }; }; - /* - * U-boot Specific Change - * - * The OTG controller must come after the USB host pair for it - * to work. This is likely due to lack of support for the USB - * PHYs. This must be manually changed after each device tree - * sync. There is no clean way to handle this in -u-boot.dtsi - * files. - */ usb20_otg: usb@ff580000 { compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", "snps,dwc2"; reg = <0x0 0xff580000 0x0 0x40000>; interrupts = ; - clocks = <&cru HCLK_OTG>; - clock-names = "otg"; + clocks = <&cru HCLK_OTG>, <&cru HCLK_OTG_PMU>; + clock-names = "otg", "otg_pmu"; dr_mode = "otg"; g-np-tx-fifo-size = <16>; g-rx-fifo-size = <280>; g-tx-fifo-size = <256 128 128 64 32 16>; + g-use-dma; phys = <&u2phy_otg>; phy-names = "usb2-phy"; status = "disabled"; }; + usb_host0_ehci: usb@ff5c0000 { + compatible = "generic-ehci"; + reg = <0x0 0xff5c0000 0x0 0x10000>; + interrupts = ; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, + <&u2phy>; + clock-names = "usbhost", "arbiter", "utmi"; + phys = <&u2phy_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host0_ohci: usb@ff5d0000 { + compatible = "generic-ohci"; + reg = <0x0 0xff5d0000 0x0 0x10000>; + interrupts = ; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, + <&u2phy>; + clock-names = "usbhost", "arbiter", "utmi"; + phys = <&u2phy_host>; + phy-names = "usb"; + status = "disabled"; + }; + gic: interrupt-controller@ff811000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -1174,6 +1317,45 @@ hdmii2c_xfer: hdmii2c-xfer { rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>, <0 RK_PA6 1 &pcfg_pull_none>; + }; + }; + + tsp { + tsp_d0: tsp-d0 { + rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>; + }; + tsp_d1: tsp-d1 { + rockchip,pins = <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; + }; + tsp_d2: tsp-d2 { + rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; + }; + tsp_d3: tsp-d3 { + rockchip,pins = <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>; + }; + tsp_d4: tsp-d4 { + rockchip,pins = <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; + }; + tsp_d5: tsp-d5 { + rockchip,pins = <2 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; + }; + tsp_d6: tsp-d6 { + rockchip,pins = <2 RK_PC1 RK_FUNC_3 &pcfg_pull_none>; + }; + tsp_d7: tsp-d7 { + rockchip,pins = <2 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; + }; + tsp_sync: tsp-sync { + rockchip,pins = <2 RK_PB7 RK_FUNC_3 &pcfg_pull_none>; + }; + tsp_clk: tsp-clk { + rockchip,pins = <3 RK_PA2 RK_FUNC_1 &pcfg_pull_none>; + }; + tsp_fail: tsp-fail { + rockchip,pins = <3 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; + }; + tsp_valid: tsp-valid { + rockchip,pins = <3 RK_PA0 RK_FUNC_1 &pcfg_pull_none>; }; };